Eliminate the ISel priority queue, which used the topological order for a
authorDan Gohman <gohman@apple.com>
Wed, 5 Nov 2008 04:14:16 +0000 (04:14 +0000)
committerDan Gohman <gohman@apple.com>
Wed, 5 Nov 2008 04:14:16 +0000 (04:14 +0000)
commit8be6bbe5bfd50945ac6c5542e0f54a0924a5db8d
treeabedd58cca5caf54d92b3093da2cc916ae679464
parentfa210d8dd1433d344d430ece5ef3efb629e992cd
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.

The impact on most targets is that AddToISelQueue calls can be simply removed.

In the x86 target, there are two additional notable changes.

The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.

Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/DAGISelHeader.h
include/llvm/CodeGen/SelectionDAG.h
lib/Target/ARM/ARMISelDAGToDAG.cpp
lib/Target/Alpha/AlphaISelDAGToDAG.cpp
lib/Target/CellSPU/SPUISelDAGToDAG.cpp
lib/Target/IA64/IA64ISelDAGToDAG.cpp
lib/Target/Mips/MipsISelDAGToDAG.cpp
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
lib/Target/Sparc/SparcISelDAGToDAG.cpp
lib/Target/X86/X86ISelDAGToDAG.cpp
utils/TableGen/DAGISelEmitter.cpp