[mips] [IAS] Add support for LAReg with identical source and destination register...
authorToma Tabacu <toma.tabacu@imgtec.com>
Mon, 22 Jun 2015 13:10:23 +0000 (13:10 +0000)
committerToma Tabacu <toma.tabacu@imgtec.com>
Mon, 22 Jun 2015 13:10:23 +0000 (13:10 +0000)
commit8204fb27acb0b5d1c32ee40af5eedde9eca811b2
tree1cc7019f603d216e4d9a0e5ba66ced2a1a1e5699
parent114489ab2446e4ebff595d7f99953f6ebcb020a9
[mips] [IAS] Add support for LAReg with identical source and destination register operands.

Summary: In this case, we're supposed to load the immediate in AT and then ADDu it with the source register and put it in the destination register.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9367

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240278 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
test/MC/Mips/mips-expansions.s