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(parent: dcfa0f7) | patch
DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap
authorTim Northover <tnorthover@apple.com>
Tue, 27 Aug 2013 13:46:45 +0000 (13:46 +0000)
committerTim Northover <tnorthover@apple.com>
Tue, 27 Aug 2013 13:46:45 +0000 (13:46 +0000)
commit5d8c2e460cac05dedf3466d630995f1475317fc9
tree9ab80c4f7be7f508466aef594c506b37ec2a6621tree | snapshot
parentdcfa0f7a408e54f15f0237daf2336df852053c6bcommit | diff
DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap

We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N),
const), but this is only valid if the bits above 16 on the source pattern are
0, the checks we were doing on this were slightly wrong before.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189348 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff | blob | history
test/CodeGen/X86/bswap.ll diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors