[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.
authorJuergen Ributzka <juergen@apple.com>
Wed, 20 Aug 2014 16:34:15 +0000 (16:34 +0000)
committerJuergen Ributzka <juergen@apple.com>
Wed, 20 Aug 2014 16:34:15 +0000 (16:34 +0000)
commit5273295751756f4537aad691cdb8a155a74db7ae
tree6ec4cd91bbcae08a8fa495db45ccbc05dcb184af
parent4b67b5a95838ba0c33546603a5f4df4400499f6d
[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.

This fixes a bug I introduced in a previous commit (r216033). Sign-/Zero-
extension from i1 cannot be folded into the ADDS/SUBS instructions. Instead both
operands have to be sign-/zero-extended with separate instructions.

Related to <rdar://problem/17913111>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216073 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64FastISel.cpp
test/CodeGen/AArch64/arm64-fast-isel-icmp.ll