Added fix in TableGen instruction decoder generation. The decoder now breaks for...
authorSilviu Baranga <silviu.baranga@arm.com>
Mon, 2 Apr 2012 15:20:39 +0000 (15:20 +0000)
committerSilviu Baranga <silviu.baranga@arm.com>
Mon, 2 Apr 2012 15:20:39 +0000 (15:20 +0000)
commit50ac2e9229044681b1c060125cf4d0ce1fc44d71
treed820cdef0787964995b9dbe3303c77968101c33c
parent5004e9849aff165bcbd953f891b402ad23bdd1ac
Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874 91177308-0d34-0410-b5e6-96231b3b80d8
test/MC/Disassembler/ARM/ldrd-armv4.txt [new file with mode: 0644]