Split fpscr into two registers: FPSCR and FPSCR_NZCV.
authorLang Hames <lhames@gmail.com>
Tue, 6 Mar 2012 00:19:55 +0000 (00:19 +0000)
committerLang Hames <lhames@gmail.com>
Tue, 6 Mar 2012 00:19:55 +0000 (00:19 +0000)
commit4f92b5e6163b16d63eb63269c2aec670b55ea19a
tree964b85f11ba8de9367f99501d06a22d7f7166755
parent923bb4117a13eac03a6ff630a108829ab767d519
Split fpscr into two registers: FPSCR and FPSCR_NZCV.

The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMBaseRegisterInfo.cpp
lib/Target/ARM/ARMFastISel.cpp
lib/Target/ARM/ARMInstrVFP.td
lib/Target/ARM/ARMRegisterInfo.td
test/CodeGen/ARM/2012-03-05-FPSCR-bug.ll [new file with mode: 0644]