This commit contains a few changes that had to go in together.
authorNadav Rotem <nadav.rotem@intel.com>
Sun, 1 Apr 2012 19:31:22 +0000 (19:31 +0000)
committerNadav Rotem <nadav.rotem@intel.com>
Sun, 1 Apr 2012 19:31:22 +0000 (19:31 +0000)
commit4ac9081c7110dbf099d682fa51c091741e763491
treef665cc901c1c40c8909558426dd8d9c24ad6301f
parent16d6eae08209251a31dae638908c79bd39620c91
This commit contains a few changes that had to go in together.

1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
   (and also scalar_to_vector).

2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src).
   Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B))

3. Optimize swizzles of shuffles:  shuff(shuff(x, y), undef) -> shuff(x, y).

4. Fix an X86ISelLowering optimization which was very bitcast-sensitive.

Code which was previously compiled to this:

movd    (%rsi), %xmm0
movdqa  .LCPI0_0(%rip), %xmm2
pshufb  %xmm2, %xmm0
movd    (%rdi), %xmm1
pshufb  %xmm2, %xmm1
pxor    %xmm0, %xmm1
pshufb  .LCPI0_1(%rip), %xmm1
movd    %xmm1, (%rdi)
ret

Now compiles to this:

movl    (%rsi), %eax
xorl    %eax, (%rdi)
ret

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153848 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/ARM/reg_sequence.ll
test/CodeGen/CellSPU/rotate_ops.ll
test/CodeGen/X86/2011-10-27-tstore.ll
test/CodeGen/X86/SwizzleShuff.ll [new file with mode: 0644]
test/CodeGen/X86/vec_shuffle-37.ll
test/CodeGen/X86/widen_shuffle-1.ll