Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively...
authorEvan Cheng <evan.cheng@apple.com>
Wed, 16 Jun 2010 07:35:02 +0000 (07:35 +0000)
committerEvan Cheng <evan.cheng@apple.com>
Wed, 16 Jun 2010 07:35:02 +0000 (07:35 +0000)
commit46df4eb46e784036cf895db271fe29e1cf2a975a
tree7a7225e258b7af507f92aec209f538b3bcf78671
parentffd33cd36494cf29a0b0c80f00ed1a51b599b31f
Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/AggressiveAntiDepBreaker.cpp
lib/CodeGen/AggressiveAntiDepBreaker.h
lib/CodeGen/CriticalAntiDepBreaker.cpp
lib/CodeGen/CriticalAntiDepBreaker.h
lib/CodeGen/IfConversion.cpp
lib/CodeGen/PostRAHazardRecognizer.cpp
lib/CodeGen/RegisterScavenging.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/ARM/ARMTargetMachine.cpp
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
test/CodeGen/Thumb2/thumb2-ifcvt2.ll