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(parent: 2129a0f) | patch
Add support for floating point base register + offset register addressing mode
authorAkira Hatanaka <ahatanaka@mips.com>
Tue, 28 Feb 2012 02:55:02 +0000 (02:55 +0000)
committerAkira Hatanaka <ahatanaka@mips.com>
Tue, 28 Feb 2012 02:55:02 +0000 (02:55 +0000)
commit44b6c715ac87505f98066fa3bf6e3e99a26b886a
tree1ed886d9d780808668b543c30dc21d16a35bbf79tree | snapshot
parent2129a0f6773b3625ddc5d541fe454a9a923cec2acommit | diff
Add support for floating point base register + offset register addressing mode
load and store instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/MipsISelDAGToDAG.cpp diff | blob | history
lib/Target/Mips/MipsISelLowering.cpp diff | blob | history
lib/Target/Mips/MipsInstrFPU.td diff | blob | history
lib/Target/Mips/MipsInstrFormats.td diff | blob | history
lib/Target/Mips/MipsInstrInfo.td diff | blob | history
lib/Target/Mips/MipsSubtarget.h diff | blob | history
test/CodeGen/Mips/fp-indexed-ls.ll [new file with mode: 0644] blob
test/CodeGen/Mips/mips64-fp-indexed-ls.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors