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(parent: 7c42ede) | patch
ARM: Constrain regclass for TSTri instruction.
authorJim Grosbach <grosbach@apple.com>
Mon, 26 Aug 2013 20:22:05 +0000 (20:22 +0000)
committerJim Grosbach <grosbach@apple.com>
Mon, 26 Aug 2013 20:22:05 +0000 (20:22 +0000)
commit383a810b129aa5120d6a7f6e88e141ec4a45f61b
tree5a9f19d6f84b1995b5419b10e12b600c536c45a0tree | snapshot
parent7c42ede04579373a2d3e124b4417d89430d541f3commit | diff
ARM: Constrain regclass for TSTri instruction.

Get the register class right for the TST instruction. This keeps the
machine verifier happy, enabling us to turn it on for another test.

rdar://12594152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMFastISel.cpp diff | blob | history
test/CodeGen/ARM/fast-isel-br-phi.ll diff | blob | history
C/C++ LLVM-based compilers that forbids OOTA behaviors