Remove custom allocation order boilerplate that is no longer needed.
authorJakob Stoklund Olesen <stoklund@2pi.dk>
Thu, 9 Jun 2011 16:56:59 +0000 (16:56 +0000)
committerJakob Stoklund Olesen <stoklund@2pi.dk>
Thu, 9 Jun 2011 16:56:59 +0000 (16:56 +0000)
commit2a9d1ca9c244aeac98044a5fc9a081ff3df7b2ff
tree49d18cc72723705aed0596cb965ecbd9942cff51
parent6f3661fdcd10a33d225502f8b112dc5b7968ef74
Remove custom allocation order boilerplate that is no longer needed.

The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.

Some targets still use custom allocation orders:

ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.

X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.

SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
14 files changed:
lib/Target/Alpha/AlphaRegisterInfo.td
lib/Target/Blackfin/BlackfinRegisterInfo.td
lib/Target/CellSPU/SPURegisterInfo.td
lib/Target/MBlaze/MBlazeRegisterInfo.td
lib/Target/MSP430/MSP430RegisterInfo.cpp
lib/Target/MSP430/MSP430RegisterInfo.td
lib/Target/Mips/MipsRegisterInfo.cpp
lib/Target/Mips/MipsRegisterInfo.td
lib/Target/PowerPC/PPCRegisterInfo.td
lib/Target/Sparc/SparcRegisterInfo.cpp
lib/Target/Sparc/SparcRegisterInfo.td
lib/Target/X86/X86RegisterInfo.cpp
lib/Target/X86/X86RegisterInfo.td
lib/Target/XCore/XCoreRegisterInfo.td