[PATCH][PPC64LE] Correct little-endian usage of vmrgh* and vmrgl*.
authorBill Schmidt <wschmidt@linux.vnet.ibm.com>
Fri, 25 Jul 2014 01:55:55 +0000 (01:55 +0000)
committerBill Schmidt <wschmidt@linux.vnet.ibm.com>
Fri, 25 Jul 2014 01:55:55 +0000 (01:55 +0000)
commit2286ae542c3e3ad92c321dde36ca8830fb5610c9
tree5d97732be80291bbfaac56d2e390af696b263874
parent65b3fca21f445abb2a01b4c7381ebb5f0f037a32
[PATCH][PPC64LE] Correct little-endian usage of vmrgh* and vmrgl*.

Because the PowerPC vmrgh* and vmrgl* instructions have a built-in
big-endian bias, it is necessary to swap their inputs in little-endian
mode when using them to implement a vector shuffle.  This was
previously missed in the vector LE implementation.

There was already logic to distinguish between unary and "normal"
vmrg* vector shuffles, so this patch extends that logic to use a third
option:  "swapped" vmrg* vector shuffles that are used for little
endian in place of the "normal" ones.

I've updated the vec-shuffle-le.ll test to check for the expected
register ordering on the generated instructions.

This bug was discovered when testing the LE and ELFv2 patches for
safety if they were backported to 3.4.  A different vectorization
decision was made in 3.4 than on mainline trunk, and that exposed the
problem.  I've verified this fix takes care of that issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213915 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCISelLowering.h
lib/Target/PowerPC/PPCInstrAltivec.td
test/CodeGen/PowerPC/vec_shuffle_le.ll