Change the generation of the vmuluwm instruction to be based on the MUL opcode.
authorKit Barton <kbarton@ca.ibm.com>
Tue, 10 Mar 2015 19:49:38 +0000 (19:49 +0000)
committerKit Barton <kbarton@ca.ibm.com>
Tue, 10 Mar 2015 19:49:38 +0000 (19:49 +0000)
commit1f9ea3a230a5cbebb20c30aad34d6cabade898e1
treecf045e7674a2c2880375549c76269087426b8412
parenta99cd39362381881c114f28263e15dd40202c729
Change the generation of the vmuluwm instruction to be based on the MUL opcode.

Phabricator review: http://reviews.llvm.org/D8185

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231827 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/IntrinsicsPowerPC.td
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCInstrAltivec.td
test/CodeGen/PowerPC/vec_mul.ll
test/CodeGen/PowerPC/vec_mul_even_odd.ll