[mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used
authorZoran Jovanovic <zoran.jovanovic@imgtec.com>
Thu, 29 Oct 2015 14:40:19 +0000 (14:40 +0000)
committerZoran Jovanovic <zoran.jovanovic@imgtec.com>
Thu, 29 Oct 2015 14:40:19 +0000 (14:40 +0000)
commit1a6d92e562fa76c0113275ef0bdc3c6077c5c5b6
treec9534c25fb9899f49bcfd5a475ab7f965dd1a75d
parent775c49859965c4b4019ff78fc2a241aad54de38c
[mips] wrong opcode for ll/sc instructions on mipsr6 when -integrated-as is used

Summary:
This commit resolves wrong opcodes for ll and sc instructions for r6 architecutres, which were generated in method MipsTargetLowering::emitAtomicBinary.

Author: Jelena.Losic

Reviewers: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D13593

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@251629 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/Mips/MipsISelLowering.cpp
test/CodeGen/Mips/atomicSCr6.ll [new file with mode: 0644]