Fix FastISel's assumption that i1 values are always zero-extended
authorDan Gohman <gohman@apple.com>
Fri, 13 Mar 2009 20:42:20 +0000 (20:42 +0000)
committerDan Gohman <gohman@apple.com>
Fri, 13 Mar 2009 20:42:20 +0000 (20:42 +0000)
commit14ea1ec2324cb595f2e035bbf54ddcd483f17c11
tree32414e0df6b4f5c9c28a4f49ed7e2990bdf511ec
parent71503710972ac747e6eaf76877cf1118d2059fce
Fix FastISel's assumption that i1 values are always zero-extended
by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/CodeGen/FastISel.h
lib/CodeGen/SelectionDAG/FastISel.cpp
lib/Target/X86/X86FastISel.cpp
test/CodeGen/X86/fast-isel-i1.ll [new file with mode: 0644]