Fix an issue of pseudo atomic instruction DAG schedule
authorMichael Liao <michael.liao@intel.com>
Tue, 22 Jan 2013 21:47:38 +0000 (21:47 +0000)
committerMichael Liao <michael.liao@intel.com>
Tue, 22 Jan 2013 21:47:38 +0000 (21:47 +0000)
commit13d08bf4159d8ffb780bb2e29a03763c17543001
tree1c8c07bc610082d790c546b17ca78bd418315d74
parent221514efe92676ce84a5e21bea91d8a6b21f9ed7
Fix an issue of pseudo atomic instruction DAG schedule

- Add list of physical registers clobbered in pseudo atomic insts
  Physical registers are clobbered when pseudo atomic instructions are
  expanded. Add them in clobber list to prevent DAG scheduler to
  mis-schedule them after these insns are declared side-effect free.
- Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86InstrCompiler.td
test/CodeGen/X86/atomic-dagsched.ll [new file with mode: 0644]