Add instruction selection support for horizontal add/sub of 256-bit floating point...
authorCraig Topper <craig.topper@gmail.com>
Fri, 2 Dec 2011 07:16:01 +0000 (07:16 +0000)
committerCraig Topper <craig.topper@gmail.com>
Fri, 2 Dec 2011 07:16:01 +0000 (07:16 +0000)
commit138a5c66b9ccaded2ee5d63b96f69349c098e49a
tree30e3657159395d604a62b43450cad0841b4926d9
parent826941a0af2c8ef695a6424cc5c712ac3df67f4c
Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145680 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avx2-phaddsub.ll [new file with mode: 0644]
test/CodeGen/X86/haddsub.ll