Do not emit intermediate register for zero FP immediate
authorRenato Golin <renato.golin@linaro.org>
Thu, 23 Oct 2014 15:31:50 +0000 (15:31 +0000)
committerRenato Golin <renato.golin@linaro.org>
Thu, 23 Oct 2014 15:31:50 +0000 (15:31 +0000)
commit06b11e36e5d0981a4da994baa78a54dbe8a9878e
treea3311e5de42a6955aab734d278ec18263d23a6d6
parent8b8e2b2f81634900a40eaa9336b8617f88b4f97e
Do not emit intermediate register for zero FP immediate

This updates check for double precision zero floating point constant to allow
use of instruction with immediate value rather than temporary register.
Currently "a == 0.0", where "a" is of "double" type generates:

vmov.i32        d16, #0x0
vcmpe.f64       d0, d16

With this change it becomes:

vcmpe.f64        d0, #0

Patch by Sergey Dmitrouk.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220486 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMISelLowering.cpp
test/CodeGen/ARM/fpcmp-f64-neon-opt.ll [new file with mode: 0644]