Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type...
authorTanya Lattner <tonic@nondot.org>
Thu, 7 Apr 2011 15:24:20 +0000 (15:24 +0000)
committerTanya Lattner <tonic@nondot.org>
Thu, 7 Apr 2011 15:24:20 +0000 (15:24 +0000)
commit0433b21c989e7d4817574b950387355fe05f59b5
tree6575a62e88e7e323f38ca9560685aa16677ed3e0
parent71001c97c6dda3df509ba4b9b37f979ea1aa8127
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/ARM/ARMISelLowering.cpp
test/CodeGen/ARM/vector-DAGCombine.ll