X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=utils%2FTableGen%2FAsmWriterEmitter.cpp;h=cc74f9ebceced78dc3c901482325b7b5a53dddb9;hp=447b7c8103956b479aba6541ae311dbdd5bc3683;hb=f7649afaba06bfd08fdd087067fc7aae43aadb9a;hpb=1132d0cc5bfd56c7fedab7c88c346958693a2f1c

diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp
index 447b7c81039..cc74f9ebcec 100644
--- a/utils/TableGen/AsmWriterEmitter.cpp
+++ b/utils/TableGen/AsmWriterEmitter.cpp
@@ -278,12 +278,15 @@ static void UnescapeString(std::string &Str) {
 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
   Record *AsmWriter = Target.getAsmWriter();
   std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+  unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
 
   O <<
   "/// printInstruction - This method is automatically generated by tablegen\n"
   "/// from the instruction set description.\n"
     "void " << Target.getName() << ClassName
-            << "::printInstruction(const MCInst *MI, raw_ostream &O) {\n";
+            << "::printInstruction(const MCInst *MI, "
+            << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
+            << "raw_ostream &O) {\n";
 
   // Build an aggregate string, and build a table of offsets into it.
   SequenceToOffsetTable<std::string> StringTable;
@@ -583,6 +586,8 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
   const auto &Registers = Target.getRegBank().getRegisters();
   std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
   bool hasAltNames = AltNameIndices.size() > 1;
+  std::string Namespace =
+      Registers.front().TheDef->getValueAsString("Namespace");
 
   O <<
   "\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
@@ -607,9 +612,9 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
     O << "  switch(AltIdx) {\n"
       << "  default: llvm_unreachable(\"Invalid register alt name index!\");\n";
     for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
-      std::string Namespace = AltNameIndices[1]->getValueAsString("Namespace");
       std::string AltName(AltNameIndices[i]->getName());
-      O << "  case " << Namespace << "::" << AltName << ":\n"
+      std::string Prefix = !Namespace.empty() ? Namespace + "::" : "";
+      O << "  case " << Prefix << AltName << ":\n"
         << "    assert(*(AsmStrs" << AltName << "+RegAsmOffset"
         << AltName << "[RegNo-1]) &&\n"
         << "           \"Invalid alt name index for register!\");\n"
@@ -724,7 +729,6 @@ public:
         ++I;
       }
     }
-    OS.flush();
 
     // Emit the string.
     O.indent(6) << "AsmString = \"" << OutString << "\";\n";
@@ -733,14 +737,13 @@ public:
     O.indent(4) << '}';
   }
 
-  bool operator==(const IAPrinter &RHS) {
+  bool operator==(const IAPrinter &RHS) const {
     if (Conds.size() != RHS.Conds.size())
       return false;
 
     unsigned Idx = 0;
-    for (std::vector<std::string>::iterator
-           I = Conds.begin(), E = Conds.end(); I != E; ++I)
-      if (*I != RHS.Conds[Idx++])
+    for (const auto &str : Conds)
+      if (str != RHS.Conds[Idx++])
         return false;
 
     return true;
@@ -759,12 +762,12 @@ static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
 
 namespace {
 struct AliasPriorityComparator {
-  typedef std::pair<CodeGenInstAlias *, int> ValueType;
+  typedef std::pair<CodeGenInstAlias, int> ValueType;
   bool operator()(const ValueType &LHS, const ValueType &RHS) {
     if (LHS.second ==  RHS.second) {
       // We don't actually care about the order, but for consistency it
       // shouldn't depend on pointer comparisons.
-      return LHS.first->TheDef->getName() < RHS.first->TheDef->getName();
+      return LHS.first.TheDef->getName() < RHS.first.TheDef->getName();
     }
 
     // Aliases with larger priorities should be considered first.
@@ -787,17 +790,17 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
   // Emit the method that prints the alias instruction.
   std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
   unsigned Variant = AsmWriter->getValueAsInt("Variant");
+  unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
 
   std::vector<Record*> AllInstAliases =
     Records.getAllDerivedDefinitions("InstAlias");
 
   // Create a map from the qualified name to a list of potential matches.
-  typedef std::set<std::pair<CodeGenInstAlias*, int>, AliasPriorityComparator>
+  typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>
       AliasWithPriority;
   std::map<std::string, AliasWithPriority> AliasMap;
   for (std::vector<Record*>::iterator
          I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
-    CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Variant, Target);
     const Record *R = *I;
     int Priority = R->getValueAsInt("EmitPriority");
     if (Priority < 1)
@@ -805,13 +808,13 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
 
     const DagInit *DI = R->getValueAsDag("ResultInst");
     const DefInit *Op = cast<DefInit>(DI->getOperator());
-    AliasMap[getQualifiedName(Op->getDef())].insert(std::make_pair(Alias,
-                                                                   Priority));
+    AliasMap[getQualifiedName(Op->getDef())].insert(
+        std::make_pair(CodeGenInstAlias(*I, Variant, Target), Priority));
   }
 
   // A map of which conditions need to be met for each instruction operand
   // before it can be matched to the mnemonic.
-  std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap;
+  std::map<std::string, std::vector<IAPrinter>> IAPrinterMap;
 
   // A list of MCOperandPredicates for all operands in use, and the reverse map
   std::vector<const Record*> MCOpPredicates;
@@ -819,25 +822,24 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
 
   for (auto &Aliases : AliasMap) {
     for (auto &Alias : Aliases.second) {
-      const CodeGenInstAlias *CGA = Alias.first;
-      unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
+      const CodeGenInstAlias &CGA = Alias.first;
+      unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
       unsigned NumResultOps =
-        CountNumOperands(CGA->ResultInst->AsmString, Variant);
+          CountNumOperands(CGA.ResultInst->AsmString, Variant);
 
       // Don't emit the alias if it has more operands than what it's aliasing.
-      if (NumResultOps < CountNumOperands(CGA->AsmString, Variant))
+      if (NumResultOps < CountNumOperands(CGA.AsmString, Variant))
         continue;
 
-      IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),
-                                     CGA->AsmString);
+      IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString);
 
       unsigned NumMIOps = 0;
-      for (auto &Operand : CGA->ResultOperands)
+      for (auto &Operand : CGA.ResultOperands)
         NumMIOps += Operand.getMINumOperands();
 
       std::string Cond;
       Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps);
-      IAP->addCond(Cond);
+      IAP.addCond(Cond);
 
       bool CantHandle = false;
 
@@ -845,7 +847,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
       for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
         std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
 
-        const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
+        const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
 
         switch (RO.Kind) {
         case CodeGenInstAlias::ResultOperand::K_Record: {
@@ -871,11 +873,11 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
           if (Rec->isSubClassOf("RegisterOperand"))
             Rec = Rec->getValueAsDef("RegClass");
           if (Rec->isSubClassOf("RegisterClass")) {
-            IAP->addCond(Op + ".isReg()");
+            IAP.addCond(Op + ".isReg()");
 
-            if (!IAP->isOpMapped(ROName)) {
-              IAP->addOperand(ROName, MIOpNum, PrintMethodIdx);
-              Record *R = CGA->ResultOperands[i].getRecord();
+            if (!IAP.isOpMapped(ROName)) {
+              IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
+              Record *R = CGA.ResultOperands[i].getRecord();
               if (R->isSubClassOf("RegisterOperand"))
                 R = R->getValueAsDef("RegClass");
               Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
@@ -883,12 +885,12 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
                                     ".contains(" + Op + ".getReg())";
             } else {
               Cond = Op + ".getReg() == MI->getOperand(" +
-                llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()";
+                     llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()";
             }
           } else {
             // Assume all printable operands are desired for now. This can be
             // overridden in the InstAlias instantiation if necessary.
-            IAP->addOperand(ROName, MIOpNum, PrintMethodIdx);
+            IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
 
             // There might be an additional predicate on the MCOperand
             unsigned Entry = MCOpPredicateMap[Rec];
@@ -901,42 +903,41 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
                 break; // No conditions on this operand at all
             }
             Cond = Target.getName() + ClassName + "ValidateMCOperand(" +
-                   Op + ", " + llvm::utostr(Entry) + ")";
+                   Op + ", STI, " + llvm::utostr(Entry) + ")";
           }
           // for all subcases of ResultOperand::K_Record:
-          IAP->addCond(Cond);
+          IAP.addCond(Cond);
           break;
         }
         case CodeGenInstAlias::ResultOperand::K_Imm: {
           // Just because the alias has an immediate result, doesn't mean the
           // MCInst will. An MCExpr could be present, for example.
-          IAP->addCond(Op + ".isImm()");
+          IAP.addCond(Op + ".isImm()");
 
-          Cond = Op + ".getImm() == "
-            + llvm::utostr(CGA->ResultOperands[i].getImm());
-          IAP->addCond(Cond);
+          Cond = Op + ".getImm() == " +
+                 llvm::utostr(CGA.ResultOperands[i].getImm());
+          IAP.addCond(Cond);
           break;
         }
         case CodeGenInstAlias::ResultOperand::K_Reg:
           // If this is zero_reg, something's playing tricks we're not
           // equipped to handle.
-          if (!CGA->ResultOperands[i].getRegister()) {
+          if (!CGA.ResultOperands[i].getRegister()) {
             CantHandle = true;
             break;
           }
 
-          Cond = Op + ".getReg() == " + Target.getName() +
-            "::" + CGA->ResultOperands[i].getRegister()->getName();
-          IAP->addCond(Cond);
+          Cond = Op + ".getReg() == " + Target.getName() + "::" +
+                 CGA.ResultOperands[i].getRegister()->getName();
+          IAP.addCond(Cond);
           break;
         }
 
-        if (!IAP) break;
         MIOpNum += RO.getMINumOperands();
       }
 
       if (CantHandle) continue;
-      IAPrinterMap[Aliases.first].push_back(IAP);
+      IAPrinterMap[Aliases.first].push_back(std::move(IAP));
     }
   }
 
@@ -949,35 +950,32 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
 
   HeaderO << "bool " << Target.getName() << ClassName
           << "::printAliasInstr(const MCInst"
-          << " *MI, raw_ostream &OS) {\n";
+          << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
+          << "raw_ostream &OS) {\n";
 
   std::string Cases;
   raw_string_ostream CasesO(Cases);
 
-  for (std::map<std::string, std::vector<IAPrinter*> >::iterator
-         I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) {
-    std::vector<IAPrinter*> &IAPs = I->second;
+  for (auto &Entry : IAPrinterMap) {
+    std::vector<IAPrinter> &IAPs = Entry.second;
     std::vector<IAPrinter*> UniqueIAPs;
 
-    for (std::vector<IAPrinter*>::iterator
-           II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) {
-      IAPrinter *LHS = *II;
+    for (auto &LHS : IAPs) {
       bool IsDup = false;
-      for (std::vector<IAPrinter*>::iterator
-             III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) {
-        IAPrinter *RHS = *III;
-        if (LHS != RHS && *LHS == *RHS) {
+      for (const auto &RHS : IAPs) {
+        if (&LHS != &RHS && LHS == RHS) {
           IsDup = true;
           break;
         }
       }
 
-      if (!IsDup) UniqueIAPs.push_back(LHS);
+      if (!IsDup)
+        UniqueIAPs.push_back(&LHS);
     }
 
     if (UniqueIAPs.empty()) continue;
 
-    CasesO.indent(2) << "case " << I->first << ":\n";
+    CasesO.indent(2) << "case " << Entry.first << ":\n";
 
     for (std::vector<IAPrinter*>::iterator
            II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
@@ -1000,8 +998,9 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
 
   if (!MCOpPredicates.empty())
     O << "static bool " << Target.getName() << ClassName
-      << "ValidateMCOperand(\n"
-      << "       const MCOperand &MCOp, unsigned PredicateIndex);\n";
+      << "ValidateMCOperand(const MCOperand &MCOp,\n"
+      << "                  const MCSubtargetInfo &STI,\n"
+      << "                  unsigned PredicateIndex);\n";
 
   O << HeaderO.str();
   O.indent(2) << "const char *AsmString;\n";
@@ -1027,9 +1026,13 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
   O << "          ++I;\n";
   O << "          int OpIdx = AsmString[I++] - 1;\n";
   O << "          int PrintMethodIdx = AsmString[I++] - 1;\n";
-  O << "          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);\n";
+  O << "          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, ";
+  O << (PassSubtarget ? "STI, " : "");
+  O << "OS);\n";
   O << "        } else\n";
-  O << "          printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n";
+  O << "          printOperand(MI, unsigned(AsmString[I++]) - 1, ";
+  O << (PassSubtarget ? "STI, " : "");
+  O << "OS);\n";
   O << "      } else {\n";
   O << "        OS << AsmString[I++];\n";
   O << "      }\n";
@@ -1046,7 +1049,9 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
   O << "void " << Target.getName() << ClassName << "::"
     << "printCustomAliasOperand(\n"
     << "         const MCInst *MI, unsigned OpIdx,\n"
-    << "         unsigned PrintMethodIdx, raw_ostream &OS) {\n";
+    << "         unsigned PrintMethodIdx,\n"
+    << (PassSubtarget ? "         const MCSubtargetInfo &STI,\n" : "")
+    << "         raw_ostream &OS) {\n";
   if (PrintMethods.empty())
     O << "  llvm_unreachable(\"Unknown PrintMethod kind\");\n";
   else {
@@ -1057,7 +1062,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
 
     for (unsigned i = 0; i < PrintMethods.size(); ++i) {
       O << "  case " << i << ":\n"
-        << "    " << PrintMethods[i] << "(MI, OpIdx, OS);\n"
+        << "    " << PrintMethods[i] << "(MI, OpIdx, "
+        << (PassSubtarget ? "STI, " : "") << "OS);\n"
         << "    break;\n";
     }
     O << "  }\n";
@@ -1066,8 +1072,9 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
 
   if (!MCOpPredicates.empty()) {
     O << "static bool " << Target.getName() << ClassName
-      << "ValidateMCOperand(\n"
-      << "       const MCOperand &MCOp, unsigned PredicateIndex) {\n"
+      << "ValidateMCOperand(const MCOperand &MCOp,\n"
+      << "                  const MCSubtargetInfo &STI,\n"
+      << "                  unsigned PredicateIndex) {\n"      
       << "  switch (PredicateIndex) {\n"
       << "  default:\n"
       << "    llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
@@ -1093,8 +1100,8 @@ AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) {
   Record *AsmWriter = Target.getAsmWriter();
   for (const CodeGenInstruction *I : Target.instructions())
     if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
-      Instructions.push_back(
-          AsmWriterInst(*I, AsmWriter->getValueAsInt("Variant")));
+      Instructions.emplace_back(*I, AsmWriter->getValueAsInt("Variant"),
+                                AsmWriter->getValueAsInt("PassSubtarget"));
 
   // Get the instruction numbering.
   NumberedInstructions = &Target.getInstructionsByEnumValue();