X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=utils%2FTableGen%2FAsmWriterEmitter.cpp;h=8e83df2009b4a16776388a504fad7a6064b24404;hp=4a36195962bd75f2ce03557cc51d8fd6e8c07f75;hb=7259f14839ab7a61f2af6e897005585b1ea4a3d4;hpb=79a1166b13f0207887ab95aae9bea08d18117f56 diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 4a36195962b..8e83df2009b 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -15,6 +15,7 @@ #include "AsmWriterInst.h" #include "CodeGenTarget.h" #include "SequenceToOffsetTable.h" +#include "llvm/ADT/SmallString.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/Debug.h" @@ -29,12 +30,14 @@ #include using namespace llvm; +#define DEBUG_TYPE "asm-writer-emitter" + namespace { class AsmWriterEmitter { RecordKeeper &Records; CodeGenTarget Target; std::map CGIAWIMap; - std::vector NumberedInstructions; + const std::vector *NumberedInstructions; std::vector Instructions; public: AsmWriterEmitter(RecordKeeper &R); @@ -47,9 +50,9 @@ private: void EmitPrintAliasInstruction(raw_ostream &O); AsmWriterInst *getAsmWriterInstByID(unsigned ID) const { - assert(ID < NumberedInstructions.size()); + assert(ID < NumberedInstructions->size()); std::map::const_iterator I = - CGIAWIMap.find(NumberedInstructions[ID]); + CGIAWIMap.find(NumberedInstructions->at(ID)); assert(I != CGIAWIMap.end() && "Didn't find inst!"); return I->second; } @@ -141,7 +144,7 @@ void AsmWriterEmitter:: FindUniqueOperandCommands(std::vector &UniqueOperandCommands, std::vector &InstIdxs, std::vector &InstOpsUsed) const { - InstIdxs.assign(NumberedInstructions.size(), ~0U); + InstIdxs.assign(NumberedInstructions->size(), ~0U); // This vector parallels UniqueOperandCommands, keeping track of which // instructions each case are used for. It is a comma separated string of @@ -150,9 +153,10 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, InstrsForCase.resize(UniqueOperandCommands.size()); InstOpsUsed.assign(UniqueOperandCommands.size(), 0); - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { const AsmWriterInst *Inst = getAsmWriterInstByID(i); - if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc. + if (!Inst) + continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc. std::string Command; if (Inst->Operands.empty()) @@ -280,15 +284,12 @@ static void UnescapeString(std::string &Str) { void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { Record *AsmWriter = Target.getAsmWriter(); std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter"); - const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr"; O << "/// printInstruction - This method is automatically generated by tablegen\n" "/// from the instruction set description.\n" "void " << Target.getName() << ClassName - << "::printInstruction(const " << MachineInstrClassName - << " *MI, raw_ostream &O) {\n"; + << "::printInstruction(const MCInst *MI, raw_ostream &O) {\n"; // Build an aggregate string, and build a table of offsets into it. SequenceToOffsetTable StringTable; @@ -301,9 +302,9 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { // Add all strings to the string table upfront so it can generate an optimized // representation. - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]]; - if (AWI != 0 && + for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { + AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)]; + if (AWI && AWI->Operands[0].OperandType == AsmWriterOperand::isLiteralTextOperand && !AWI->Operands[0].Str.empty()) { @@ -316,10 +317,10 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { StringTable.layout(); unsigned MaxStringIdx = 0; - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]]; + for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { + AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)]; unsigned Idx; - if (AWI == 0) { + if (!AWI) { // Something not handled by the asmwriter printer. Idx = ~0U; } else if (AWI->Operands[0].OperandType != @@ -379,7 +380,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { BitsLeft -= NumBits; // Remove the info about this operand. - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { if (AsmWriterInst *Inst = getAsmWriterInstByID(i)) if (!Inst->Operands.empty()) { unsigned NumOps = NumInstOpsHandled[InstIdxs[i]]; @@ -398,9 +399,9 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { // We always emit at least one 32-bit table. A second table is emitted if // more bits are needed. O<<" static const uint32_t OpInfo[] = {\n"; - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { O << " " << (OpcodeInfo[i] & 0xffffffff) << "U,\t// " - << NumberedInstructions[i]->TheDef->getName() << "\n"; + << NumberedInstructions->at(i)->TheDef->getName() << "\n"; } // Add a dummy entry so the array init doesn't end with a comma. O << " 0U\n"; @@ -412,9 +413,9 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { O << " static const uint" << ((BitsLeft < 16) ? "32" : (BitsLeft < 24) ? "16" : "8") << "_t OpInfo2[] = {\n"; - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { O << " " << (OpcodeInfo[i] >> 32) << "U,\t// " - << NumberedInstructions[i]->TheDef->getName() << "\n"; + << NumberedInstructions->at(i)->TheDef->getName() << "\n"; } // Add a dummy entry so the array init doesn't end with a comma. O << " 0U\n"; @@ -549,8 +550,8 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, Reg.TheDef->getValueAsListOfStrings("AltNames"); if (AltNames.size() <= Idx) PrintFatalError(Reg.TheDef->getLoc(), - (Twine("Register definition missing alt name for '") + - AltName + "'.").str()); + "Register definition missing alt name for '" + + AltName + "'."); AsmName = AltNames[Idx]; } } @@ -605,8 +606,8 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { << " switch(AltIdx) {\n" << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) { - StringRef Namespace = AltNameIndices[1]->getValueAsString("Namespace"); - StringRef AltName(AltNameIndices[i]->getName()); + std::string Namespace = AltNameIndices[1]->getValueAsString("Namespace"); + std::string AltName(AltNameIndices[i]->getName()); O << " case " << Namespace << "::" << AltName << ":\n" << " AsmStrs = AsmStrs" << AltName << ";\n" @@ -711,19 +712,6 @@ public: return true; } - - bool operator()(const IAPrinter &RHS) { - if (Conds.size() < RHS.Conds.size()) - return true; - - unsigned Idx = 0; - for (std::vector::iterator - I = Conds.begin(), E = Conds.end(); I != E; ++I) - if (*I != RHS.Conds[Idx++]) - return *I < RHS.Conds[Idx++]; - - return false; - } }; } // end anonymous namespace @@ -764,9 +752,6 @@ static unsigned CountResultNumOperands(StringRef AsmString) { void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { Record *AsmWriter = Target.getAsmWriter(); - if (!AsmWriter->getValueAsBit("isMCAsmWriter")) - return; - O << "\n#ifdef PRINT_ALIAS_INSTR\n"; O << "#undef PRINT_ALIAS_INSTR\n\n"; @@ -851,7 +836,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); // FIXME: We may need to handle these situations. delete IAP; - IAP = 0; + IAP = nullptr; CantHandle = true; break; } @@ -990,7 +975,7 @@ AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { AsmWriter->getValueAsInt("OperandSpacing"))); // Get the instruction numbering. - NumberedInstructions = Target.getInstructionsByEnumValue(); + NumberedInstructions = &Target.getInstructionsByEnumValue(); // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not // all machine instructions are necessarily being printed, so there may be