X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=test%2FCodeGen%2FX86%2F2007-11-30-LoadFolding-Bug.ll;h=8e315f4d80ff426b2a0697ae012c802a04f7e949;hp=7afb9bf369bdf52bf061c930e5a731a766c39fa8;hb=7476f9c5134a7170ca53561d20e9a19adef251f8;hpb=2b85dc3544f4611d07bd1fdf2fe4081e3b0793fd diff --git a/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll b/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll index 7afb9bf369b..8e315f4d80f 100644 --- a/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll +++ b/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll @@ -1,5 +1,6 @@ -; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -disable-correct-folding -stats |& \ -; RUN: grep {1 .*folded into instructions} +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; Increment in loop bb.i28.i adjusted to 2, to prevent loop reversal from +; kicking in. declare fastcc void @rdft(i32, i32, double*, i32*, double*) @@ -9,28 +10,32 @@ entry: bb.i5: ; preds = %bb.i5, %entry %nfft_init.0.i = phi i32 [ 1, %entry ], [ %tmp7.i3, %bb.i5 ] ; [#uses=1] + %foo = phi i1 [1, %entry], [0, %bb.i5] %tmp7.i3 = shl i32 %nfft_init.0.i, 1 ; [#uses=2] - br i1 false, label %bb.i5, label %mp_unexp_mp2d.exit.i + br i1 %foo, label %bb.i5, label %mp_unexp_mp2d.exit.i mp_unexp_mp2d.exit.i: ; preds = %bb.i5 - br i1 false, label %cond_next.i, label %cond_true.i + br i1 %foo, label %cond_next.i, label %cond_true.i cond_true.i: ; preds = %mp_unexp_mp2d.exit.i ret void cond_next.i: ; preds = %mp_unexp_mp2d.exit.i %tmp22.i = sdiv i32 0, 2 ; [#uses=2] - br i1 false, label %cond_true29.i, label %cond_next36.i + br i1 %foo, label %cond_true29.i, label %cond_next36.i cond_true29.i: ; preds = %cond_next.i ret void cond_next36.i: ; preds = %cond_next.i store i32 %tmp22.i, i32* null, align 4 - %tmp8.i14.i = select i1 false, i32 1, i32 0 ; [#uses=1] + %tmp8.i14.i = select i1 %foo, i32 1, i32 0 ; [#uses=1] br label %bb.i28.i bb.i28.i: ; preds = %bb.i28.i, %cond_next36.i +; CHECK: %bb.i28.i +; CHECK: addl $2 +; CHECK: addl $-2 %j.0.reg2mem.0.i16.i = phi i32 [ 0, %cond_next36.i ], [ %indvar.next39.i, %bb.i28.i ] ; [#uses=2] %din_addr.1.reg2mem.0.i17.i = phi double [ 0.000000e+00, %cond_next36.i ], [ %tmp16.i25.i, %bb.i28.i ] ; [#uses=1] %tmp1.i18.i = fptosi double %din_addr.1.reg2mem.0.i17.i to i32 ; [#uses=2] @@ -38,16 +43,16 @@ bb.i28.i: ; preds = %bb.i28.i, %cond_next36.i %x.0.i21.i = select i1 %tmp4.i19.i, i32 %tmp1.i18.i, i32 0 ; [#uses=1] %tmp41.sum.i = add i32 %j.0.reg2mem.0.i16.i, 2 ; [#uses=0] %tmp1213.i23.i = sitofp i32 %x.0.i21.i to double ; [#uses=1] - %tmp15.i24.i = sub double 0.000000e+00, %tmp1213.i23.i ; [#uses=1] - %tmp16.i25.i = mul double 0.000000e+00, %tmp15.i24.i ; [#uses=1] - %indvar.next39.i = add i32 %j.0.reg2mem.0.i16.i, 1 ; [#uses=2] + %tmp15.i24.i = fsub double 0.000000e+00, %tmp1213.i23.i ; [#uses=1] + %tmp16.i25.i = fmul double 0.000000e+00, %tmp15.i24.i ; [#uses=1] + %indvar.next39.i = add i32 %j.0.reg2mem.0.i16.i, 2 ; [#uses=2] %exitcond40.i = icmp eq i32 %indvar.next39.i, %tmp8.i14.i ; [#uses=1] br i1 %exitcond40.i, label %mp_unexp_d2mp.exit29.i, label %bb.i28.i mp_unexp_d2mp.exit29.i: ; preds = %bb.i28.i %tmp46.i = sub i32 0, %tmp22.i ; [#uses=1] store i32 %tmp46.i, i32* null, align 4 - br i1 false, label %bb.i.i, label %mp_sqrt_init.exit + br i1 %exitcond40.i, label %bb.i.i, label %mp_sqrt_init.exit bb.i.i: ; preds = %bb.i.i, %mp_unexp_d2mp.exit29.i br label %bb.i.i @@ -56,7 +61,7 @@ mp_sqrt_init.exit: ; preds = %mp_unexp_d2mp.exit29.i tail call fastcc void @mp_mul_csqu( i32 0, double* %tmp1fft ) tail call fastcc void @rdft( i32 0, i32 -1, double* null, i32* %ip, double* %w ) tail call fastcc void @mp_mul_d2i( i32 0, i32 %radix, i32 0, double* %tmp1fft, i32* %tmp2 ) - br i1 false, label %cond_false.i, label %cond_true36.i + br i1 %exitcond40.i, label %cond_false.i, label %cond_true36.i cond_true36.i: ; preds = %mp_sqrt_init.exit ret void