X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=test%2FBitcode%2FterminatorInstructions.3.2.ll;h=ba0f5ade2cc1a3b595417d701fd8b8931edf7c9a;hp=1bdbdcc4c98a811325624ef3a50ff1c8436f7aa2;hb=5f843038fbc274615ddc113e421c379552e212c8;hpb=72bffaafb407be750f29277ef049fc8a0a165637

diff --git a/test/Bitcode/terminatorInstructions.3.2.ll b/test/Bitcode/terminatorInstructions.3.2.ll
index 1bdbdcc4c98..ba0f5ade2cc 100644
--- a/test/Bitcode/terminatorInstructions.3.2.ll
+++ b/test/Bitcode/terminatorInstructions.3.2.ll
@@ -1,5 +1,4 @@
-; RUN: llvm-dis < %s.bc| FileCheck %s
-; RUN: verify-uselistorder < %s.bc
+; RUN:  llvm-dis < %s.bc| FileCheck %s
 
 ; TerminatorOperations.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
 ; The test checks that LLVM does not misread terminator instructions from
@@ -9,10 +8,10 @@ define i32 @condbr(i1 %cond){
 entry:
 ; CHECK: br i1 %cond, label %TrueLabel, label %FalseLabel
   br i1 %cond, label %TrueLabel, label %FalseLabel
-
+  
   TrueLabel:
   ret i32 1
-
+  
   FalseLabel:
   ret i32 0
 }
@@ -21,7 +20,7 @@ define i32 @uncondbr(){
 entry:
 ; CHECK: br label %uncondLabel
   br label %uncondLabel
-
+  
   uncondLabel:
   ret i32 1
 }
@@ -30,10 +29,10 @@ define i32 @indirectbr(i8* %Addr){
 entry:
 ; CHECK: indirectbr i8* %Addr, [label %bb1, label %bb2]
   indirectbr i8* %Addr, [ label %bb1, label %bb2 ]
-
+  
   bb1:
   ret i32 1
-
+  
   bb2:
   ret i32 0
 }
@@ -42,7 +41,36 @@ define void @unreachable(){
 entry:
 ; CHECK: unreachable
   unreachable
+  
+  ret void
+}
+
+define i32 @retInstr(){
+entry:
+; CHECK: ret i32 1 
+  ret i32 1 
+}
 
+define void @retInstr2(){
+entry:
+; CHECK: ret void 
   ret void
 }
 
+define i32 @switchInstr(i32 %x){
+entry:
+; CHECK: switch i32 %x, label %label3 [
+  switch i32 %x, label %label3 [
+; CHECK-NEXT: i32 1, label %label1   
+  i32 1, label %label1
+; CHECK-NEXT: i32 2, label %label2  
+  i32 2, label %label2
+  ]
+label1:
+  ret i32 1
+label2:
+  ret i32 2
+label3:
+  ret i32 0
+}
+