X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FTarget%2FTargetInstrInfo.cpp;h=17e9ac8e3f9924e6f879fdf387bd666bfb2b092c;hp=a3131bb319f556766df98d3dd8a16c87eaca655d;hb=4ee451de366474b9c228b4e5fa573795a715216d;hpb=0f5918a0b6dba521be3c254718d1f41fad6b8d30

diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index a3131bb319f..17e9ac8e3f9 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -1,12 +1,13 @@
 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
 //===----------------------------------------------------------------------===//
 //
+// This file implements the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
@@ -14,52 +15,85 @@
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Constant.h"
 #include "llvm/DerivedTypes.h"
+using namespace llvm;
 
-namespace llvm {
+/// findTiedToSrcOperand - Returns the operand that is tied to the specified
+/// dest operand. Returns -1 if there isn't one.
+int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
+  for (unsigned i = 0, e = numOperands; i != e; ++i) {
+    if (i == OpNum)
+      continue;
+    if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum)
+      return i;
+  }
+  return -1;
+}
 
-// External object describing the machine instructions
-// Initialized only when the TargetMachine class is created
-// and reset when that class is destroyed.
-// 
-const TargetInstrDescriptor* TargetInstrDescriptors = 0;
 
 TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
-				 unsigned DescSize,
-				 unsigned NumRealOpCodes)
-  : desc(Desc), descSize(DescSize), numRealOpCodes(NumRealOpCodes) {
-  // FIXME: TargetInstrDescriptors should not be global
-  assert(TargetInstrDescriptors == NULL && desc != NULL
-         && "TargetMachine data structure corrupt; maybe you tried to create another TargetMachine? (only one may exist in a program)");
-  TargetInstrDescriptors = desc;	// initialize global variable
+                                 unsigned numOpcodes)
+  : desc(Desc), NumOpcodes(numOpcodes) {
 }
 
 TargetInstrInfo::~TargetInstrInfo() {
-  TargetInstrDescriptors = NULL;	// reset global variable
 }
 
-bool TargetInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
-					       int64_t intValue) const {
-  // First, check if opCode has an immed field.
-  bool isSignExtended;
-  uint64_t maxImmedValue = maxImmedConstant(opCode, isSignExtended);
-  if (maxImmedValue != 0)
-    {
-      // NEED TO HANDLE UNSIGNED VALUES SINCE THEY MAY BECOME MUCH
-      // SMALLER AFTER CASTING TO SIGN-EXTENDED int, short, or char.
-      // See CreateUIntSetInstruction in SparcInstrInfo.cpp.
-      
-      // Now check if the constant fits
-      if (intValue <= (int64_t) maxImmedValue &&
-	  intValue >= -((int64_t) maxImmedValue+1))
-	return true;
-    }
-  
-  return false;
+// commuteInstruction - The default implementation of this method just exchanges
+// operand 1 and 2.
+MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
+  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
+         "This only knows how to commute register operands so far");
+  unsigned Reg1 = MI->getOperand(1).getReg();
+  unsigned Reg2 = MI->getOperand(2).getReg();
+  bool Reg1IsKill = MI->getOperand(1).isKill();
+  bool Reg2IsKill = MI->getOperand(2).isKill();
+  MI->getOperand(2).setReg(Reg1);
+  MI->getOperand(1).setReg(Reg2);
+  if (Reg1IsKill)
+    MI->getOperand(2).setIsKill();
+  else
+    MI->getOperand(2).unsetIsKill();
+  if (Reg2IsKill)
+    MI->getOperand(1).setIsKill();
+  else
+    MI->getOperand(1).unsetIsKill();
+  return MI;
 }
 
-bool TargetInstrInfo::ConstantTypeMustBeLoaded(const Constant* CV) const {
-  assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType()));
-  return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType()));
+bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
+                                const std::vector<MachineOperand> &Pred) const {
+  bool MadeChange = false;
+  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  if (TID->Flags & M_PREDICABLE) {
+    for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
+      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+        MachineOperand &MO = MI->getOperand(i);
+        if (MO.isRegister()) {
+          MO.setReg(Pred[j].getReg());
+          MadeChange = true;
+        } else if (MO.isImmediate()) {
+          MO.setImm(Pred[j].getImmedValue());
+          MadeChange = true;
+        } else if (MO.isMachineBasicBlock()) {
+          MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());
+          MadeChange = true;
+        }
+        ++j;
+      }
+    }
+  }
+  return MadeChange;
 }
 
-} // End llvm namespace
+bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
+  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  if (TID->Flags & M_TERMINATOR_FLAG) {
+    // Conditional branch is a special case.
+    if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0)
+      return true;
+    if ((TID->Flags & M_PREDICABLE) == 0)
+      return true;
+    return !isPredicated(MI);
+  }
+  return false;
+}