X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FTarget%2FSparc%2FSparcCodeEmitter.cpp;h=98239bfc400082d9079567591f8ac130794a3263;hp=9bfe31fe496928af651d312b0aa199d666899ed4;hb=9f85dccfc64b5f0b0c63ddfa0a42d8615aa1fcb3;hpb=38aceb871478893bfa87f94c2cb3a344a4c8c2df diff --git a/lib/Target/Sparc/SparcCodeEmitter.cpp b/lib/Target/Sparc/SparcCodeEmitter.cpp index 9bfe31fe496..98239bfc400 100644 --- a/lib/Target/Sparc/SparcCodeEmitter.cpp +++ b/lib/Target/Sparc/SparcCodeEmitter.cpp @@ -12,9 +12,8 @@ // //===---------------------------------------------------------------------===// -#define DEBUG_TYPE "jit" #include "Sparc.h" -#include "MCTargetDesc/SparcBaseInfo.h" +#include "MCTargetDesc/SparcMCExpr.h" #include "SparcRelocations.h" #include "SparcTargetMachine.h" #include "llvm/ADT/Statistic.h" @@ -25,6 +24,8 @@ using namespace llvm; +#define DEBUG_TYPE "jit" + STATISTIC(NumEmitted, "Number of machine instructions emitted"); namespace { @@ -39,7 +40,7 @@ class SparcCodeEmitter : public MachineFunctionPass { const std::vector *MCPEs; bool IsPIC; - void getAnalysisUsage(AnalysisUsage &AU) const { + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired (); MachineFunctionPass::getAnalysisUsage(AU); } @@ -48,13 +49,13 @@ class SparcCodeEmitter : public MachineFunctionPass { public: SparcCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) - : MachineFunctionPass(ID), JTI(0), II(0), TD(0), - TM(tm), MCE(mce), MCPEs(0), + : MachineFunctionPass(ID), JTI(nullptr), II(nullptr), TD(nullptr), + TM(tm), MCE(mce), MCPEs(nullptr), IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} - bool runOnMachineFunction(MachineFunction &MF); + bool runOnMachineFunction(MachineFunction &MF) override; - virtual const char *getPassName() const { + const char *getPassName() const override { return "Sparc Machine Code Emitter"; } @@ -72,6 +73,15 @@ private: unsigned getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const; + unsigned getCallTargetOpValue(const MachineInstr &MI, + unsigned) const; + unsigned getBranchTargetOpValue(const MachineInstr &MI, + unsigned) const; + unsigned getBranchPredTargetOpValue(const MachineInstr &MI, + unsigned) const; + unsigned getBranchOnRegTargetOpValue(const MachineInstr &MI, + unsigned) const; + void emitWord(unsigned Word); unsigned getRelocation(const MachineInstr &MI, @@ -90,10 +100,10 @@ bool SparcCodeEmitter::runOnMachineFunction(MachineFunction &MF) { SparcTargetMachine &Target = static_cast( const_cast(MF.getTarget())); - JTI = Target.getJITInfo(); - II = Target.getInstrInfo(); - TD = Target.getDataLayout(); - Subtarget = &TM.getSubtarget (); + JTI = Target.getSubtargetImpl()->getJITInfo(); + II = Target.getSubtargetImpl()->getInstrInfo(); + TD = Target.getSubtargetImpl()->getDataLayout(); + Subtarget = &TM.getSubtarget(); MCPEs = &MF.getConstantPool()->getConstants(); JTI->Initialize(MF, IsPIC); MCE.setModuleInfo(&getAnalysis ()); @@ -136,7 +146,8 @@ void SparcCodeEmitter::emitInstruction(MachineBasicBlock::instr_iterator MI, } break; } - case TargetOpcode::PROLOG_LABEL: + case TargetOpcode::CFI_INSTRUCTION: + break; case TargetOpcode::EH_LABEL: { MCE.emitLabel(MI->getOperand(0).getMCSymbol()); break; @@ -166,7 +177,8 @@ void SparcCodeEmitter::emitWord(unsigned Word) { unsigned SparcCodeEmitter::getMachineOpValue(const MachineInstr &MI, const MachineOperand &MO) const { if (MO.isReg()) - return TM.getRegisterInfo()->getEncodingValue(MO.getReg()); + return TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue( + MO.getReg()); else if (MO.isImm()) return static_cast(MO.getImm()); else if (MO.isGlobal()) @@ -181,20 +193,44 @@ unsigned SparcCodeEmitter::getMachineOpValue(const MachineInstr &MI, llvm_unreachable("Unable to encode MachineOperand!"); return 0; } +unsigned SparcCodeEmitter::getCallTargetOpValue(const MachineInstr &MI, + unsigned opIdx) const { + const MachineOperand MO = MI.getOperand(opIdx); + return getMachineOpValue(MI, MO); +} + +unsigned SparcCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI, + unsigned opIdx) const { + const MachineOperand MO = MI.getOperand(opIdx); + return getMachineOpValue(MI, MO); +} + +unsigned SparcCodeEmitter::getBranchPredTargetOpValue(const MachineInstr &MI, + unsigned opIdx) const { + const MachineOperand MO = MI.getOperand(opIdx); + return getMachineOpValue(MI, MO); +} + +unsigned SparcCodeEmitter::getBranchOnRegTargetOpValue(const MachineInstr &MI, + unsigned opIdx) const { + const MachineOperand MO = MI.getOperand(opIdx); + return getMachineOpValue(MI, MO); +} + unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI, const MachineOperand &MO) const { unsigned TF = MO.getTargetFlags(); switch (TF) { default: - case SPII::MO_NO_FLAG: break; - case SPII::MO_LO: return SP::reloc_sparc_lo; - case SPII::MO_HI: return SP::reloc_sparc_hi; - case SPII::MO_H44: - case SPII::MO_M44: - case SPII::MO_L44: - case SPII::MO_HH: - case SPII::MO_HM: assert(0 && "FIXME: Implement Medium/Large code model."); + case SparcMCExpr::VK_Sparc_None: break; + case SparcMCExpr::VK_Sparc_LO: return SP::reloc_sparc_lo; + case SparcMCExpr::VK_Sparc_HI: return SP::reloc_sparc_hi; + case SparcMCExpr::VK_Sparc_H44: return SP::reloc_sparc_h44; + case SparcMCExpr::VK_Sparc_M44: return SP::reloc_sparc_m44; + case SparcMCExpr::VK_Sparc_L44: return SP::reloc_sparc_l44; + case SparcMCExpr::VK_Sparc_HH: return SP::reloc_sparc_hh; + case SparcMCExpr::VK_Sparc_HM: return SP::reloc_sparc_hm; } unsigned Opc = MI.getOpcode();