X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsSubtarget.h;h=ef8e27a5e1a7903f692aded5ebcb7cb12bc5428d;hp=bff656ff12577a382ea66d631682cb5fcf29d2e1;hb=b40edb9a1b91426f8eaec32956bb4f844b142684;hpb=d5c4b1a5587d12627668da4236873ef828283fd6

diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h
index bff656ff125..ef8e27a5e1a 100644
--- a/lib/Target/Mips/MipsSubtarget.h
+++ b/lib/Target/Mips/MipsSubtarget.h
@@ -14,6 +14,7 @@
 #ifndef MIPSSUBTARGET_H
 #define MIPSSUBTARGET_H
 
+#include "MipsJITInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
@@ -132,6 +133,8 @@ protected:
   MipsTargetMachine *TM;
 
   Triple TargetTriple;
+
+  MipsJITInfo JITInfo;
 public:
   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
                              AntiDepBreakMode& Mode,
@@ -248,6 +251,8 @@ public:
   /// specify which component of the system provides it. Hardware, software, and
   /// hybrid implementations are all valid.
   bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
+
+  MipsJITInfo *getJITInfo() { return &JITInfo; }
 };
 } // End llvm namespace