X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsSubtarget.cpp;h=4d2dc07644ffc3cc66ae04225af4e9150151d4e3;hp=fa71106f5b88b16d90d7c583b4140bf7d2f2ba57;hb=7b82808e13c883184639e81a26a837c6246eb57f;hpb=ea27d2f50b1666732f2345fcb39be5f71485aa83 diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index fa71106f5b8..4d2dc07644f 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -33,100 +33,62 @@ using namespace llvm; // FIXME: Maybe this should be on by default when Mips16 is specified // -static cl::opt Mixed16_32( - "mips-mixed-16-32", - cl::init(false), - cl::desc("Allow for a mixture of Mips16 " - "and Mips32 code in a single source file"), - cl::Hidden); - -static cl::opt Mips_Os16( - "mips-os16", - cl::init(false), - cl::desc("Compile all functions that don' use " - "floating point as Mips 16"), - cl::Hidden); +static cl::opt + Mixed16_32("mips-mixed-16-32", cl::init(false), + cl::desc("Allow for a mixture of Mips16 " + "and Mips32 code in a single output file"), + cl::Hidden); + +static cl::opt Mips_Os16("mips-os16", cl::init(false), + cl::desc("Compile all functions that don't use " + "floating point as Mips 16"), + cl::Hidden); + +static cl::opt Mips16HardFloat("mips16-hard-float", cl::NotHidden, + cl::desc("Enable mips16 hard float."), + cl::init(false)); static cl::opt -Mips16HardFloat("mips16-hard-float", cl::NotHidden, - cl::desc("MIPS: mips16 hard float enable."), - cl::init(false)); + Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden, + cl::desc("Enable mips16 constant islands."), + cl::init(true)); static cl::opt -Mips16ConstantIslands( - "mips16-constant-islands", cl::NotHidden, - cl::desc("MIPS: mips16 constant islands enable."), - cl::init(true)); - -/// Select the Mips CPU for the given triple and cpu name. -/// FIXME: Merge with the copy in MipsMCTargetDesc.cpp -static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) { - if (CPU.empty() || CPU == "generic") { - Triple TheTriple(TT); - if (TheTriple.getArch() == Triple::mips || - TheTriple.getArch() == Triple::mipsel) - CPU = "mips32"; - else - CPU = "mips64"; - } - return CPU; -} + GPOpt("mgpopt", cl::Hidden, + cl::desc("Enable gp-relative addressing of mips small data items")); void MipsSubtarget::anchor() { } -MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, +MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, bool little, - Reloc::Model _RM, MipsTargetMachine *_TM) - : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32), - MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), - IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), - HasCnMips(false), IsLinux(true), HasMips3_32(false), HasMips4_32(false), - HasMips4_32r2(false), HasBitCount(false), InMips16Mode(false), - InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), - HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), - HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM), - TargetTriple(TT) { - std::string CPUName = CPU; - CPUName = selectMipsCPU(TT, CPUName); - - // Parse features string. - ParseSubtargetFeatures(CPUName, FS); - - if (InMips16Mode && !TM->Options.UseSoftFloat) { - // Hard float for mips16 means essentially to compile as soft float - // but to use a runtime library for soft float that is written with - // native mips32 floating point instructions (those runtime routines - // run in mips32 hard float mode). - TM->Options.UseSoftFloat = true; - TM->Options.FloatABIType = FloatABI::Soft; - InMips16HardFloat = true; - } + const MipsTargetMachine &TM) + : MipsGenSubtargetInfo(TargetTuple(TT), CPU, FS), + MipsArchVersion(MipsDefault), IsLittle(little), IsSoftFloat(false), + IsSingleFloat(false), IsFPXX(false), NoABICalls(false), IsFP64bit(false), + UseOddSPReg(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), + HasCnMips(false), HasMips3_32(false), HasMips3_32r2(false), + HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), + InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), + InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), + AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false), + UseTCCInDIV(false), HasEVA(false), TM(TM), TargetTriple(TT), TSInfo(), + InstrInfo( + MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))), + FrameLowering(MipsFrameLowering::create(*this)), + TLInfo(MipsTargetLowering::create(TM, *this)) { PreviousInMips16Mode = InMips16Mode; - // Initialize scheduling itinerary for the specified CPU. - InstrItins = getInstrItineraryForCPU(CPUName); + if (MipsArchVersion == MipsDefault) + MipsArchVersion = Mips32; - // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and - // MIPS-V. They have not been tested and currently exist for the integrated - // assembler only. + // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not + // been tested and currently exist for the integrated assembler only. if (MipsArchVersion == Mips1) report_fatal_error("Code generation for MIPS-I is not implemented", false); - if (MipsArchVersion == Mips2) - report_fatal_error("Code generation for MIPS-II is not implemented", false); - if (MipsArchVersion == Mips3) - report_fatal_error("Code generation for MIPS-III is not implemented", - false); if (MipsArchVersion == Mips5) report_fatal_error("Code generation for MIPS-V is not implemented", false); - // Assert exactly one ABI was chosen. - assert(MipsABI != UnknownABI); - assert((((getFeatureBits() & Mips::FeatureO32) != 0) + - ((getFeatureBits() & Mips::FeatureEABI) != 0) + - ((getFeatureBits() & Mips::FeatureN32) != 0) + - ((getFeatureBits() & Mips::FeatureN64) != 0)) == 1); - // Check if Architecture and ABI are compatible. assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) || (isGP64bit() && (isABI_N32() || isABI_N64()))) && @@ -137,6 +99,12 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, "See -mattr=+fp64.", false); + if (!isABI_O32() && !useOddSPReg()) + report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); + + if (IsFPXX && (isABI_N32() || isABI_N64())) + report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); + if (hasMips32r6()) { StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; @@ -146,79 +114,59 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, report_fatal_error(ISA + " is not compatible with the DSP ASE", false); } - // Is the target system Linux ? - if (TT.find("linux") == std::string::npos) - IsLinux = false; + if (NoABICalls && TM.getRelocationModel() == Reloc::PIC_) + report_fatal_error("position-independent code requires '-mabicalls'"); // Set UseSmallSection. - // TODO: Investigate the IsLinux check. I suspect it's really checking for - // bare-metal. - UseSmallSection = !IsLinux && (RM == Reloc::Static); - // set some subtarget specific features - if (inMips16Mode()) - HasBitCount=false; + UseSmallSection = GPOpt; + if (!NoABICalls && GPOpt) { + errs() << "warning: cannot use small-data accesses for '-mabicalls'" + << "\n"; + UseSmallSection = false; + } } -bool -MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, - TargetSubtargetInfo::AntiDepBreakMode &Mode, - RegClassVector &CriticalPathRCs) const { - Mode = TargetSubtargetInfo::ANTIDEP_NONE; +/// This overrides the PostRAScheduler bit in the SchedModel for any CPU. +bool MipsSubtarget::enablePostRAScheduler() const { return true; } + +void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { CriticalPathRCs.clear(); - CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass - : &Mips::GPR32RegClass); - return OptLevel >= CodeGenOpt::Aggressive; + CriticalPathRCs.push_back(isGP64bit() ? + &Mips::GPR64RegClass : &Mips::GPR32RegClass); } -//FIXME: This logic for reseting the subtarget along with -// the helper classes can probably be simplified but there are a lot of -// cases so we will defer rewriting this to later. -// -void MipsSubtarget::resetSubtarget(MachineFunction *MF) { - bool ChangeToMips16 = false, ChangeToNoMips16 = false; - DEBUG(dbgs() << "resetSubtargetFeatures" << "\n"); - AttributeSet FnAttrs = MF->getFunction()->getAttributes(); - ChangeToMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex, - "mips16"); - ChangeToNoMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex, - "nomips16"); - assert (!(ChangeToMips16 & ChangeToNoMips16) && - "mips16 and nomips16 specified on the same function"); - if (ChangeToMips16) { - if (PreviousInMips16Mode) - return; - OverrideMode = Mips16Override; - PreviousInMips16Mode = true; - TM->setHelperClassesMips16(); - return; - } else if (ChangeToNoMips16) { - if (!PreviousInMips16Mode) - return; - OverrideMode = NoMips16Override; - PreviousInMips16Mode = false; - TM->setHelperClassesMipsSE(); - return; - } else { - if (OverrideMode == NoOverride) - return; - OverrideMode = NoOverride; - DEBUG(dbgs() << "back to default" << "\n"); - if (inMips16Mode() && !PreviousInMips16Mode) { - TM->setHelperClassesMips16(); - PreviousInMips16Mode = true; - } else if (!inMips16Mode() && PreviousInMips16Mode) { - TM->setHelperClassesMipsSE(); - PreviousInMips16Mode = false; - } - return; - } +CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { + return CodeGenOpt::Aggressive; } -bool MipsSubtarget::mipsSEUsesSoftFloat() const { - return TM->Options.UseSoftFloat && !InMips16HardFloat; +MipsSubtarget & +MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, + const TargetMachine &TM) { + std::string CPUName = + MIPS_MC::selectMipsCPU(TargetTuple(TM.getTargetTriple()), CPU); + + // Parse features string. + ParseSubtargetFeatures(CPUName, FS); + // Initialize scheduling itinerary for the specified CPU. + InstrItins = getInstrItineraryForCPU(CPUName); + + if (InMips16Mode && !IsSoftFloat) + InMips16HardFloat = true; + + return *this; } bool MipsSubtarget::useConstantIslands() { DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n"); return Mips16ConstantIslands; } + +Reloc::Model MipsSubtarget::getRelocationModel() const { + return TM.getRelocationModel(); +} + +bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); } +bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); } +bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); } +bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); } +const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }