X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FTarget%2FMips%2FMipsRegisterInfo.td;h=74dfa4fe7d9cd5cd51e08c0c6ceb46a4de3cd887;hp=db00b0dbe44e5ba6cb4dfc57ccaeaa6358dfe526;hb=663e484df9b12e2366ffb625dd3d594ca416e39f;hpb=01eaf907b09828ed9fc497d7a8d48192e486849b diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index db00b0dbe44..74dfa4fe7d9 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -1,4 +1,4 @@ -//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===// +//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -10,49 +10,83 @@ //===----------------------------------------------------------------------===// // Declarations that describe the MIPS register file //===----------------------------------------------------------------------===// +let Namespace = "Mips" in { +def sub_32 : SubRegIndex<32>; +def sub_64 : SubRegIndex<64>; +def sub_lo : SubRegIndex<32>; +def sub_hi : SubRegIndex<32, 32>; +def sub_dsp16_19 : SubRegIndex<4, 16>; +def sub_dsp20 : SubRegIndex<1, 20>; +def sub_dsp21 : SubRegIndex<1, 21>; +def sub_dsp22 : SubRegIndex<1, 22>; +def sub_dsp23 : SubRegIndex<1, 23>; +} + +class Unallocatable { + bit isAllocatable = 0; +} // We have banks of 32 registers each. -class MipsReg : Register { - field bits<5> Num; +class MipsReg Enc, string n> : Register { + let HWEncoding = Enc; let Namespace = "Mips"; } -class MipsRegWithSubRegs subregs> +class MipsRegWithSubRegs Enc, string n, list subregs> : RegisterWithSubRegs { - field bits<5> Num; + let HWEncoding = Enc; let Namespace = "Mips"; } // Mips CPU Registers -class MipsGPRReg num, string n> : MipsReg { - let Num = num; +class MipsGPRReg Enc, string n> : MipsReg; + +// Mips 64-bit CPU Registers +class Mips64GPRReg Enc, string n, list subregs> + : MipsRegWithSubRegs { + let SubRegIndices = [sub_32]; } // Mips 32-bit FPU Registers -class FPR num, string n> : MipsReg { - let Num = num; -} +class FPR Enc, string n> : MipsReg; // Mips 64-bit (aliased) FPU Registers -let Namespace = "Mips" in { -def sub_fpeven : SubRegIndex; -def sub_fpodd : SubRegIndex; +class AFPR Enc, string n, list subregs> + : MipsRegWithSubRegs { + let SubRegIndices = [sub_lo, sub_hi]; + let CoveredBySubRegs = 1; } -class AFPR num, string n, list subregs> - : MipsRegWithSubRegs { - let Num = num; - let SubRegIndices = [sub_fpeven, sub_fpodd]; + +class AFPR64 Enc, string n, list subregs> + : MipsRegWithSubRegs { + let SubRegIndices = [sub_lo, sub_hi]; + let CoveredBySubRegs = 1; +} + +// Mips 128-bit (aliased) MSA Registers +class AFPR128 Enc, string n, list subregs> + : MipsRegWithSubRegs { + let SubRegIndices = [sub_64]; } +// Accumulator Registers +class ACCReg Enc, string n, list subregs> + : MipsRegWithSubRegs { + let SubRegIndices = [sub_lo, sub_hi]; + let CoveredBySubRegs = 1; +} + +// Mips Hardware Registers +class HWR Enc, string n> : MipsReg; + //===----------------------------------------------------------------------===// // Registers //===----------------------------------------------------------------------===// let Namespace = "Mips" in { - // General Purpose Registers - def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>; - def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; + def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; + def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; @@ -79,97 +113,206 @@ let Namespace = "Mips" in { def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; - def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>; - def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>; - def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>; - def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>; + def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; + def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; + def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; + def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; + + // General Purpose 64-bit Registers + def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; + def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; + def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; + def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; + def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; + def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; + def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; + def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; + def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; + def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; + def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; + def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; + def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; + def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; + def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; + def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; + def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; + def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; + def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; + def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; + def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; + def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; + def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; + def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; + def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; + def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; + def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; + def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; + def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; + def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; + def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; + def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; /// Mips Single point precision FPU Registers - def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>; - def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>; - def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>; - def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>; - def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>; - def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>; - def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>; - def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>; - def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>; - def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>; - def F10 : FPR<10, "F10">, DwarfRegNum<[42]>; - def F11 : FPR<11, "F11">, DwarfRegNum<[43]>; - def F12 : FPR<12, "F12">, DwarfRegNum<[44]>; - def F13 : FPR<13, "F13">, DwarfRegNum<[45]>; - def F14 : FPR<14, "F14">, DwarfRegNum<[46]>; - def F15 : FPR<15, "F15">, DwarfRegNum<[47]>; - def F16 : FPR<16, "F16">, DwarfRegNum<[48]>; - def F17 : FPR<17, "F17">, DwarfRegNum<[49]>; - def F18 : FPR<18, "F18">, DwarfRegNum<[50]>; - def F19 : FPR<19, "F19">, DwarfRegNum<[51]>; - def F20 : FPR<20, "F20">, DwarfRegNum<[52]>; - def F21 : FPR<21, "F21">, DwarfRegNum<[53]>; - def F22 : FPR<22, "F22">, DwarfRegNum<[54]>; - def F23 : FPR<23, "F23">, DwarfRegNum<[55]>; - def F24 : FPR<24, "F24">, DwarfRegNum<[56]>; - def F25 : FPR<25, "F25">, DwarfRegNum<[57]>; - def F26 : FPR<26, "F26">, DwarfRegNum<[58]>; - def F27 : FPR<27, "F27">, DwarfRegNum<[59]>; - def F28 : FPR<28, "F28">, DwarfRegNum<[60]>; - def F29 : FPR<29, "F29">, DwarfRegNum<[61]>; - def F30 : FPR<30, "F30">, DwarfRegNum<[62]>; - def F31 : FPR<31, "F31">, DwarfRegNum<[63]>; + foreach I = 0-31 in + def F#I : FPR, DwarfRegNum<[!add(I, 32)]>; + + // Higher half of 64-bit FP registers. + foreach I = 0-31 in + def F_HI#I : FPR, DwarfRegNum<[!add(I, 32)]>; /// Mips Double point precision FPU Registers (aliased /// with the single precision to hold 64 bit values) - def D0 : AFPR< 0, "F0", [F0, F1]>; - def D1 : AFPR< 2, "F2", [F2, F3]>; - def D2 : AFPR< 4, "F4", [F4, F5]>; - def D3 : AFPR< 6, "F6", [F6, F7]>; - def D4 : AFPR< 8, "F8", [F8, F9]>; - def D5 : AFPR<10, "F10", [F10, F11]>; - def D6 : AFPR<12, "F12", [F12, F13]>; - def D7 : AFPR<14, "F14", [F14, F15]>; - def D8 : AFPR<16, "F16", [F16, F17]>; - def D9 : AFPR<18, "F18", [F18, F19]>; - def D10 : AFPR<20, "F20", [F20, F21]>; - def D11 : AFPR<22, "F22", [F22, F23]>; - def D12 : AFPR<24, "F24", [F24, F25]>; - def D13 : AFPR<26, "F26", [F26, F27]>; - def D14 : AFPR<28, "F28", [F28, F29]>; - def D15 : AFPR<30, "F30", [F30, F31]>; + foreach I = 0-15 in + def D#I : AFPR("F"#!shl(I, 1)), + !cast("F"#!add(!shl(I, 1), 1))]>; + + /// Mips Double point precision FPU Registers in MFP64 mode. + foreach I = 0-31 in + def D#I#_64 : AFPR64("F"#I), !cast("F_HI"#I)]>, + DwarfRegNum<[!add(I, 32)]>; + + /// Mips MSA registers + /// MSA and FPU cannot both be present unless the FPU has 64-bit registers + foreach I = 0-31 in + def W#I : AFPR128("D"#I#"_64")]>, + DwarfRegNum<[!add(I, 32)]>; // Hi/Lo registers - def HI : Register<"hi">, DwarfRegNum<[64]>; - def LO : Register<"lo">, DwarfRegNum<[65]>; + def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>; + def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>; + def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>; + def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>; + def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>; + def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>; + def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>; + def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>; + + let SubRegIndices = [sub_32] in { + def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; + def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; + } + + // FP control registers. + foreach I = 0-31 in + def FCR#I : MipsReg<#I, ""#I>; + + // FP condition code registers. + foreach I = 0-7 in + def FCC#I : MipsReg<#I, "fcc"#I>; + + // COP2 registers. + foreach I = 0-31 in + def COP2#I : MipsReg<#I, ""#I>; + + // COP3 registers. + foreach I = 0-31 in + def COP3#I : MipsReg<#I, ""#I>; + + // PC register + def PC : Register<"pc">; + + // Hardware register $29 + foreach I = 0-31 in + def HWR#I : MipsReg<#I, ""#I>; + + // Accum registers + foreach I = 0-3 in + def AC#I : ACCReg<#I, "ac"#I, + [!cast("LO"#I), !cast("HI"#I)]>; + + def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; + + // DSP-ASE control register fields. + def DSPPos : Register<"">; + def DSPSCount : Register<"">; + def DSPCarry : Register<"">; + def DSPEFI : Register<"">; + def DSPOutFlag16_19 : Register<"">; + def DSPOutFlag20 : Register<"">; + def DSPOutFlag21 : Register<"">; + def DSPOutFlag22 : Register<"">; + def DSPOutFlag23 : Register<"">; + def DSPCCond : Register<"">; + + let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, + sub_dsp23] in + def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, + DSPOutFlag21, DSPOutFlag22, + DSPOutFlag23]>; + + // MSA-ASE control registers. + def MSAIR : MipsReg<0, "0">; + def MSACSR : MipsReg<1, "1">; + def MSAAccess : MipsReg<2, "2">; + def MSASave : MipsReg<3, "3">; + def MSAModify : MipsReg<4, "4">; + def MSARequest : MipsReg<5, "5">; + def MSAMap : MipsReg<6, "6">; + def MSAUnmap : MipsReg<7, "7">; + + // Octeon multiplier and product registers + def MPL0 : MipsReg<0, "mpl0">; + def MPL1 : MipsReg<1, "mpl1">; + def MPL2 : MipsReg<2, "mpl2">; + def P0 : MipsReg<0, "p0">; + def P1 : MipsReg<1, "p1">; + def P2 : MipsReg<2, "p2">; - // Status flags register - def FCR31 : Register<"31">; } //===----------------------------------------------------------------------===// // Register Classes //===----------------------------------------------------------------------===// -def CPURegs : RegisterClass<"Mips", [i32], 32, +class GPR32Class regTypes> : + RegisterClass<"Mips", regTypes, 32, (add + // Reserved + ZERO, AT, // Return Values and Arguments - [V0, V1, A0, A1, A2, A3, + V0, V1, A0, A1, A2, A3, // Not preserved across procedure calls - T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, + T0, T1, T2, T3, T4, T5, T6, T7, // Callee save S0, S1, S2, S3, S4, S5, S6, S7, + // Not preserved across procedure calls + T8, T9, // Reserved - ZERO, AT, K0, K1, GP, SP, FP, RA]> -{ - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - CPURegsClass::iterator - CPURegsClass::allocation_order_end(const MachineFunction &MF) const { - // The last 8 registers on the list above are reserved - return end()-8; - } - }]; -} + K0, K1, GP, SP, FP, RA)>; + +def GPR32 : GPR32Class<[i32]>; +def DSPR : GPR32Class<[v4i8, v2i16]>; + +def GPR64 : RegisterClass<"Mips", [i64], 64, (add +// Reserved + ZERO_64, AT_64, + // Return Values and Arguments + V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, + // Not preserved across procedure calls + T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, + // Callee save + S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, + // Not preserved across procedure calls + T8_64, T9_64, + // Reserved + K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; + +def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add + // Return Values and Arguments + V0, V1, A0, A1, A2, A3, + // Callee save + S0, S1)>; + +def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add + // Return Values and Arguments + V0, V1, A0, A1, A2, A3, + // Callee save + S0, S1, + SP)>; + +def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; + +def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; // 64bit fp: // * FGR64 - 32 64-bit registers @@ -178,87 +321,261 @@ def CPURegs : RegisterClass<"Mips", [i32], 32, // 32bit fp: // * FGR32 - 16 32-bit even registers // * FGR32 - 32 32-bit registers (single float only mode) -def FGR32 : RegisterClass<"Mips", [f32], 32, +def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; + +def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, + Unallocatable; + +def AFGR64 : RegisterClass<"Mips", [f64], 64, (add // Return Values and Arguments - [F0, F1, F2, F3, F12, F13, F14, F15, + D0, D1, // Not preserved across procedure calls - F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19, - // Callee save - F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, - // Reserved - F31]> -{ - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - - static const unsigned MIPS_FGR32[] = { - Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13, - Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7, - Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17, - Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, - Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, - Mips::F30 - }; - - static const unsigned MIPS_SVR4_FGR32[] = { - Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4, - Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18, - Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, - }; - - FGR32Class::iterator - FGR32Class::allocation_order_begin(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const MipsSubtarget &Subtarget = TM.getSubtarget(); - - if (Subtarget.isMips32() || Subtarget.isSingleFloat()) - return MIPS_FGR32; - else - return MIPS_SVR4_FGR32; - } - - FGR32Class::iterator - FGR32Class::allocation_order_end(const MachineFunction &MF) const { - const TargetMachine &TM = MF.getTarget(); - const MipsSubtarget &Subtarget = TM.getSubtarget(); - - if (Subtarget.isMips32() || Subtarget.isSingleFloat()) - return MIPS_FGR32 + (sizeof(MIPS_FGR32) / sizeof(unsigned)); - else - return MIPS_SVR4_FGR32 + (sizeof(MIPS_SVR4_FGR32) / sizeof(unsigned)); - } - }]; -} - -def AFGR64 : RegisterClass<"Mips", [f64], 64, + D2, D3, D4, D5, // Return Values and Arguments - [D0, D1, D6, D7, + D6, D7, // Not preserved across procedure calls - D2, D3, D4, D5, D8, D9, + D8, D9, // Callee save - D10, D11, D12, D13, D14, - // Reserved - D15]> -{ - let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)]; - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - AFGR64Class::iterator - AFGR64Class::allocation_order_end(const MachineFunction &MF) const { - // The last register on the list above is reserved - return end()-1; - } - }]; -} - -// Condition Register for floating point operations -def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>; + D10, D11, D12, D13, D14, D15)>; + +def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; + +// Used to reserve odd registers when given -mattr=+nooddspreg +// FIXME: Remove double precision registers from this set. +def OddSP : RegisterClass<"Mips", [f32], 32, + (add (decimate (sequence "F%u", 1, 31), 2), + (decimate (sequence "F_HI%u", 1, 31), 2), + (decimate (sequence "D%u", 1, 15), 2), + (decimate (sequence "D%u_64", 1, 31), 2))>, + Unallocatable; + +// FP control registers. +def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, + Unallocatable; + +// FP condition code registers. +def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, + Unallocatable; + +// MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers. +// This class allows us to represent this in codegen patterns. +def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>; + +def MSA128B: RegisterClass<"Mips", [v16i8], 128, + (sequence "W%u", 0, 31)>; +def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, + (sequence "W%u", 0, 31)>; +def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, + (sequence "W%u", 0, 31)>; +def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, + (sequence "W%u", 0, 31)>; + +def MSACtrl: RegisterClass<"Mips", [i32], 32, (add + MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; // Hi/Lo Registers -def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>; +def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; +def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; +def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; +def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; +def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; +def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; + +// Hardware registers +def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>, + Unallocatable; + +// Accumulator Registers +def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { + let Size = 64; +} + +def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { + let Size = 128; +} + +def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { + let Size = 64; +} + +def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; + +// Coprocessor 2 registers. +def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>, + Unallocatable; + +// Coprocessor 3 registers. +def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>, + Unallocatable; + +// Octeon multiplier and product registers +def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>, + Unallocatable; +def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>, + Unallocatable; + +// Register Operands. + +class MipsAsmRegOperand : AsmOperandClass { + let ParserMethod = "ParseAnyRegister"; +} + +def GPR64AsmOperand : MipsAsmRegOperand { + let Name = "GPR64AsmReg"; + let PredicateMethod = "isGPRAsmReg"; +} + +def GPR32AsmOperand : MipsAsmRegOperand { + let Name = "GPR32AsmReg"; + let PredicateMethod = "isGPRAsmReg"; +} + +def ACC64DSPAsmOperand : MipsAsmRegOperand { + let Name = "ACC64DSPAsmReg"; + let PredicateMethod = "isACCAsmReg"; +} + +def HI32DSPAsmOperand : MipsAsmRegOperand { + let Name = "HI32DSPAsmReg"; + let PredicateMethod = "isACCAsmReg"; +} + +def LO32DSPAsmOperand : MipsAsmRegOperand { + let Name = "LO32DSPAsmReg"; + let PredicateMethod = "isACCAsmReg"; +} + +def CCRAsmOperand : MipsAsmRegOperand { + let Name = "CCRAsmReg"; +} + +def AFGR64AsmOperand : MipsAsmRegOperand { + let Name = "AFGR64AsmReg"; + let PredicateMethod = "isFGRAsmReg"; +} + +def FGR64AsmOperand : MipsAsmRegOperand { + let Name = "FGR64AsmReg"; + let PredicateMethod = "isFGRAsmReg"; +} + +def FGR32AsmOperand : MipsAsmRegOperand { + let Name = "FGR32AsmReg"; + let PredicateMethod = "isFGRAsmReg"; +} + +def FGRH32AsmOperand : MipsAsmRegOperand { + let Name = "FGRH32AsmReg"; + let PredicateMethod = "isFGRAsmReg"; +} + +def FCCRegsAsmOperand : MipsAsmRegOperand { + let Name = "FCCAsmReg"; +} + +def MSA128AsmOperand : MipsAsmRegOperand { + let Name = "MSA128AsmReg"; +} + +def MSACtrlAsmOperand : MipsAsmRegOperand { + let Name = "MSACtrlAsmReg"; +} + +def GPR32Opnd : RegisterOperand { + let ParserMatchClass = GPR32AsmOperand; +} + +def GPR64Opnd : RegisterOperand { + let ParserMatchClass = GPR64AsmOperand; +} + +def DSPROpnd : RegisterOperand { + let ParserMatchClass = GPR32AsmOperand; +} + +def CCROpnd : RegisterOperand { + let ParserMatchClass = CCRAsmOperand; +} + +def HWRegsAsmOperand : MipsAsmRegOperand { + let Name = "HWRegsAsmReg"; +} + +def COP2AsmOperand : MipsAsmRegOperand { + let Name = "COP2AsmReg"; +} + +def COP3AsmOperand : MipsAsmRegOperand { + let Name = "COP3AsmReg"; +} + +def HWRegsOpnd : RegisterOperand { + let ParserMatchClass = HWRegsAsmOperand; +} + +def AFGR64Opnd : RegisterOperand { + let ParserMatchClass = AFGR64AsmOperand; +} + +def FGR64Opnd : RegisterOperand { + let ParserMatchClass = FGR64AsmOperand; +} + +def FGR32Opnd : RegisterOperand { + let ParserMatchClass = FGR32AsmOperand; +} + +def FGRCCOpnd : RegisterOperand { + // The assembler doesn't use register classes so we can re-use + // FGR32AsmOperand. + let ParserMatchClass = FGR32AsmOperand; +} + +def FGRH32Opnd : RegisterOperand { + let ParserMatchClass = FGRH32AsmOperand; +} + +def FCCRegsOpnd : RegisterOperand { + let ParserMatchClass = FCCRegsAsmOperand; +} + +def LO32DSPOpnd : RegisterOperand { + let ParserMatchClass = LO32DSPAsmOperand; +} + +def HI32DSPOpnd : RegisterOperand { + let ParserMatchClass = HI32DSPAsmOperand; +} + +def ACC64DSPOpnd : RegisterOperand { + let ParserMatchClass = ACC64DSPAsmOperand; +} + +def COP2Opnd : RegisterOperand { + let ParserMatchClass = COP2AsmOperand; +} + +def COP3Opnd : RegisterOperand { + let ParserMatchClass = COP3AsmOperand; +} + +def MSA128BOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128HOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128WOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128DOpnd : RegisterOperand { + let ParserMatchClass = MSA128AsmOperand; +} + +def MSA128CROpnd : RegisterOperand { + let ParserMatchClass = MSACtrlAsmOperand; +}