X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FTarget%2FIA64%2FIA64ISelDAGToDAG.cpp;h=739ae3115fbe16217474cb47d575d286cb0803d8;hp=f79496db77def3f067cb6f26b0c878620022abda;hb=dac237e18209b697a8ba122d0ddd9cad4dfba1f8;hpb=056292fd738924f3f7703725d8f630983794b5a5 diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp index f79496db77d..739ae3115fb 100644 --- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp +++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp @@ -26,9 +26,9 @@ #include "llvm/Intrinsics.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" -#include -#include +#include "llvm/Support/raw_ostream.h" using namespace llvm; namespace { @@ -37,11 +37,10 @@ namespace { /// instructions for SelectionDAG operations. /// class IA64DAGToDAGISel : public SelectionDAGISel { - IA64TargetLowering IA64Lowering; unsigned GlobalBaseReg; public: explicit IA64DAGToDAGISel(IA64TargetMachine &TM) - : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {} + : SelectionDAGISel(TM) {} virtual bool runOnFunction(Function &Fn) { // Make sure we re-emit a set of the global base reg if necessary @@ -100,7 +99,7 @@ void IA64DAGToDAGISel::InstructionSelect() { DEBUG(BB->dump()); // Select target instructions for the DAG. - SelectRoot(); + SelectRoot(*CurDAG); CurDAG->RemoveDeadNodes(); } @@ -109,10 +108,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { SDValue Chain = N->getOperand(0); SDValue Tmp1 = N->getOperand(0); SDValue Tmp2 = N->getOperand(1); - AddToISelQueue(Chain); - - AddToISelQueue(Tmp1); - AddToISelQueue(Tmp2); + DebugLoc dl = N->getDebugLoc(); bool isFP=false; @@ -147,26 +143,28 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { if(!isFP) { // first, load the inputs into FP regs. TmpF1 = - SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0); + SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp1), 0); Chain = TmpF1.getValue(1); TmpF2 = - SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0); + SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, Tmp2), 0); Chain = TmpF2.getValue(1); // next, convert the inputs to FP if(isSigned) { TmpF3 = - SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF1), 0); Chain = TmpF3.getValue(1); TmpF4 = - SDValue(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXF, dl, MVT::f64, TmpF2), 0); Chain = TmpF4.getValue(1); } else { // is unsigned TmpF3 = - SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF1), + 0); Chain = TmpF3.getValue(1); TmpF4 = - SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0); + SDValue(CurDAG->getTargetNode(IA64::FCVTXUFS1, dl, MVT::f64, TmpF2), + 0); Chain = TmpF4.getValue(1); } @@ -179,11 +177,11 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { // we start by computing an approximate reciprocal (good to 9 bits?) // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate) if(isFP) - TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1, - TmpF3, TmpF4), 0); + TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS0, dl, MVT::f64, + MVT::i1, TmpF3, TmpF4), 0); else - TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1, - TmpF3, TmpF4), 0); + TmpF5 = SDValue(CurDAG->getTargetNode(IA64::FRCPAS1, dl, MVT::f64, + MVT::i1, TmpF3, TmpF4), 0); TmpPR = TmpF5.getValue(1); Chain = TmpF5.getValue(2); @@ -191,7 +189,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { SDValue minusB; if(isModulus) { // for remainders, it'll be handy to have // copies of -input_b - minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, MVT::i64, + minusB = SDValue(CurDAG->getTargetNode(IA64::SUB, dl, MVT::i64, CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0); Chain = minusB.getValue(1); } @@ -199,19 +197,19 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { SDValue TmpE0, TmpY1, TmpE1, TmpY2; SDValue OpsE0[] = { TmpF4, TmpF5, F1, TmpPR }; - TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, + TmpE0 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64, OpsE0, 4), 0); Chain = TmpE0.getValue(1); SDValue OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR }; - TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpY1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsY1, 4), 0); Chain = TmpY1.getValue(1); SDValue OpsE1[] = { TmpE0, TmpE0, F0, TmpPR }; - TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpE1 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsE1, 4), 0); Chain = TmpE1.getValue(1); SDValue OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR }; - TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpY2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsY2, 4), 0); Chain = TmpY2.getValue(1); @@ -222,30 +220,30 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { SDValue TmpE2, TmpY3, TmpQ0, TmpR0; SDValue OpsE2[] = { TmpE1, TmpE1, F0, TmpPR }; - TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpE2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsE2, 4), 0); Chain = TmpE2.getValue(1); SDValue OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR }; - TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpY3 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsY3, 4), 0); Chain = TmpY3.getValue(1); SDValue OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR }; TmpQ0 = - SDValue(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec! - OpsQ0, 4), 0); + SDValue(CurDAG->getTargetNode(IA64::CFMADS1, dl, // double prec! + MVT::f64, OpsQ0, 4), 0); Chain = TmpQ0.getValue(1); SDValue OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR }; TmpR0 = - SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec! - OpsR0, 4), 0); + SDValue(CurDAG->getTargetNode(IA64::CFNMADS1, dl, // double prec! + MVT::f64, OpsR0, 4), 0); Chain = TmpR0.getValue(1); // we want Result to have the same target register as the frcpa, so // we two-address hack it. See the comment "for this to work..." on // page 48 of Intel application note #245415 SDValue Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR }; - Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg! - Ops, 5); + Result = CurDAG->getTargetNode(IA64::TCFMADS0, dl, // d.p. s0 rndg! + MVT::f64, Ops, 5); Chain = SDValue(Result, 1); return Result; // XXX: early exit! } else { // this is *not* an FP divide, so there's a bit left to do: @@ -253,11 +251,11 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { SDValue TmpQ2, TmpR2, TmpQ3, TmpQ; SDValue OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR }; - TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64, + TmpQ2 = SDValue(CurDAG->getTargetNode(IA64::CFMAS1, dl, MVT::f64, OpsQ2, 4), 0); Chain = TmpQ2.getValue(1); SDValue OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR }; - TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64, + TmpR2 = SDValue(CurDAG->getTargetNode(IA64::CFNMAS1, dl, MVT::f64, OpsR2, 4), 0); Chain = TmpR2.getValue(1); @@ -265,7 +263,7 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { // should two-address hack it. See the comment "for this to work..." on page // 48 of Intel application note #245415 SDValue OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR }; - TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64, + TmpQ3 = SDValue(CurDAG->getTargetNode(IA64::TCFMAS1, dl, MVT::f64, OpsQ3, 5), 0); Chain = TmpQ3.getValue(1); @@ -274,26 +272,27 @@ SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) { // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0. if(isSigned) - TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, + TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, dl, MVT::f64, TmpQ3), 0); else - TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, + TmpQ = SDValue(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, dl, MVT::f64, TmpQ3), 0); Chain = TmpQ.getValue(1); if(isModulus) { SDValue FPminusB = - SDValue(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0); + SDValue(CurDAG->getTargetNode(IA64::SETFSIG, dl, MVT::f64, minusB), + 0); Chain = FPminusB.getValue(1); SDValue Remainder = - SDValue(CurDAG->getTargetNode(IA64::XMAL, MVT::f64, + SDValue(CurDAG->getTargetNode(IA64::XMAL, dl, MVT::f64, TmpQ, FPminusB, TmpF1), 0); Chain = Remainder.getValue(1); - Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder); + Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, Remainder); Chain = SDValue(Result, 1); } else { // just an integer divide - Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ); + Result = CurDAG->getTargetNode(IA64::GETFSIG, dl, MVT::i64, TmpQ); Chain = SDValue(Result, 1); } @@ -307,6 +306,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.getNode(); if (N->isMachineOpcode()) return NULL; // Already selected. + DebugLoc dl = Op.getDebugLoc(); switch (N->getOpcode()) { default: break; @@ -315,10 +315,8 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { SDValue Chain = N->getOperand(0); SDValue InFlag; // Null incoming flag value. - AddToISelQueue(Chain); if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag InFlag = N->getOperand(2); - AddToISelQueue(InFlag); } unsigned CallOpcode; @@ -339,27 +337,26 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { // load the branch target (function)'s entry point and GP, // branch (call) then restore the GP SDValue FnDescriptor = N->getOperand(1); - AddToISelQueue(FnDescriptor); // load the branch target's entry point [mem] and // GP value [mem+8] SDValue targetEntryPoint= - SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, + SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, FnDescriptor, CurDAG->getEntryNode()), 0); Chain = targetEntryPoint.getValue(1); SDValue targetGPAddr= - SDValue(CurDAG->getTargetNode(IA64::ADDS, MVT::i64, + SDValue(CurDAG->getTargetNode(IA64::ADDS, dl, MVT::i64, FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0); Chain = targetGPAddr.getValue(1); SDValue targetGP = - SDValue(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other, + SDValue(CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64,MVT::Other, targetGPAddr, CurDAG->getEntryNode()), 0); Chain = targetGP.getValue(1); - Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag); + Chain = CurDAG->getCopyToReg(Chain, dl, IA64::r1, targetGP, InFlag); InFlag = Chain.getValue(1); - Chain = CurDAG->getCopyToReg(Chain, IA64::B6, + Chain = CurDAG->getCopyToReg(Chain, dl, IA64::B6, targetEntryPoint, InFlag); // FLAG these? InFlag = Chain.getValue(1); @@ -369,11 +366,11 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { // Finally, once everything is setup, emit the call itself if (InFlag.getNode()) - Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, - CallOperand, InFlag), 0); + Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other, + MVT::Flag, CallOperand, InFlag), 0); else // there might be no arguments - Chain = SDValue(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, - CallOperand, Chain), 0); + Chain = SDValue(CurDAG->getTargetNode(CallOpcode, dl, MVT::Other, + MVT::Flag, CallOperand, Chain), 0); InFlag = Chain.getValue(1); std::vector CallResults; @@ -388,8 +385,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { case IA64ISD::GETFD: { SDValue Input = N->getOperand(0); - AddToISelQueue(Input); - return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input); + return CurDAG->getTargetNode(IA64::GETFD, dl, MVT::i64, Input); } case ISD::FDIV: @@ -405,10 +401,10 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { SDValue V; ConstantFPSDNode* N2 = cast(N); if (N2->getValueAPF().isPosZero()) { - V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64); + V = CurDAG->getCopyFromReg(Chain, dl, IA64::F0, MVT::f64); } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ? APFloat(+1.0f) : APFloat(+1.0))) { - V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64); + V = CurDAG->getCopyFromReg(Chain, dl, IA64::F1, MVT::f64); } else assert(0 && "Unexpected FP constant!"); @@ -422,7 +418,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)); else - return CurDAG->getTargetNode(IA64::MOV, MVT::i64, + return CurDAG->getTargetNode(IA64::MOV, dl, MVT::i64, CurDAG->getTargetFrameIndex(FI, MVT::i64)); } @@ -432,7 +428,7 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { Constant *C = CP->getConstVal(); SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64, CP->getAlignment()); - return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ? + return CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, // ? CurDAG->getRegister(IA64::r1, MVT::i64), CPI); } @@ -440,10 +436,10 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { GlobalValue *GV = cast(N)->getGlobal(); SDValue GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64); SDValue Tmp = - SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, + SDValue(CurDAG->getTargetNode(IA64::ADDL_GA, dl, MVT::i64, CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0); - return CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, Tmp, + return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, MVT::Other, Tmp, CurDAG->getEntryNode()); } @@ -452,11 +448,11 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { SDValue EA = CurDAG->getTargetExternalSymbol( cast(N)->getSymbol(), MVT::i64); - SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64, + SDValue Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, dl, MVT::i64, CurDAG->getRegister(IA64::r1, MVT::i64), EA); - return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp); + return CurDAG->getTargetNode(IA64::LD8, dl, MVT::i64, Tmp); } */ @@ -464,8 +460,6 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { LoadSDNode *LD = cast(N); SDValue Chain = LD->getChain(); SDValue Address = LD->getBasePtr(); - AddToISelQueue(Chain); - AddToISelQueue(Address); MVT TypeBeingLoaded = LD->getMemoryVT(); unsigned Opc; @@ -478,9 +472,11 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { case MVT::i1: { // this is a bool Opc = IA64::LD1; // first we load a byte, then compare for != 0 if(N->getValueType(0) == MVT::i1) { // XXX: early exit! - return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, - SDValue(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0), - CurDAG->getRegister(IA64::r0, MVT::i64), + return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other, + SDValue(CurDAG->getTargetNode(Opc, dl, + MVT::i64, + Address), 0), + CurDAG->getRegister(IA64::r0, MVT::i64), Chain); } /* otherwise, we want to load a bool into something bigger: LD1 @@ -504,8 +500,6 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { StoreSDNode *ST = cast(N); SDValue Address = ST->getBasePtr(); SDValue Chain = ST->getChain(); - AddToISelQueue(Address); - AddToISelQueue(Chain); unsigned Opc; if (ISD::isNON_TRUNCStore(N)) { @@ -514,13 +508,12 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { case MVT::i1: { // this is a bool Opc = IA64::ST1; // we store either 0 or 1 as a byte // first load zero! - SDValue Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64); + SDValue Initial = CurDAG->getCopyFromReg(Chain, dl, IA64::r0, MVT::i64); Chain = Initial.getValue(1); // then load 1 into the same reg iff the predicate to store is 1 SDValue Tmp = ST->getValue(); - AddToISelQueue(Tmp); Tmp = - SDValue(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial, + SDValue(CurDAG->getTargetNode(IA64::TPCADDS, dl, MVT::i64, Initial, CurDAG->getTargetConstant(1, MVT::i64), Tmp), 0); @@ -541,16 +534,12 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { SDValue N1 = N->getOperand(1); SDValue N2 = N->getOperand(2); - AddToISelQueue(N1); - AddToISelQueue(N2); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain); } case ISD::BRCOND: { SDValue Chain = N->getOperand(0); SDValue CC = N->getOperand(1); - AddToISelQueue(Chain); - AddToISelQueue(CC); MachineBasicBlock *Dest = cast(N->getOperand(2))->getBasicBlock(); //FIXME - we do NOT need long branches all the time @@ -564,14 +553,12 @@ SDNode *IA64DAGToDAGISel::Select(SDValue Op) { unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ? IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP; SDValue N0 = N->getOperand(0); - AddToISelQueue(N0); return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0); } case ISD::BR: // FIXME: we don't need long branches all the time! SDValue N0 = N->getOperand(0); - AddToISelQueue(N0); return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other, N->getOperand(1), N0); }