X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FTarget%2FAlpha%2FAlphaRegisterInfo.cpp;h=f1e651c6a805894ee2eea08146f981a482a3d17f;hp=4ae8761fecb9bed6fa8c6eacfc7c2b4a8259d505;hb=c25e7581b9b8088910da31702d4ca21c4734c6d7;hpb=65b889ffb559bb8f2d45cbaf5f3f624a841c3dbf diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 4ae8761fecb..f1e651c6a80 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -2,12 +2,12 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // -// This file contains the Alpha implementation of the MRegisterInfo class. +// This file contains the Alpha implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// @@ -25,11 +25,14 @@ #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include -#include using namespace llvm; //These describe LDAx @@ -51,98 +54,46 @@ static long getLower16(long l) return l - h * IMM_MULT; } -static int getUID() +AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) + : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), + TII(tii), curgpdist(0) { - static int id = 0; - return ++id; } -AlphaRegisterInfo::AlphaRegisterInfo() - : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP) -{ -} - -void -AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned SrcReg, int FrameIdx, - const TargetRegisterClass *RC) const { - //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; - //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); - if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); - else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); - else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); - else - abort(); +const unsigned* AlphaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) + const { + static const unsigned CalleeSavedRegs[] = { + Alpha::R9, Alpha::R10, + Alpha::R11, Alpha::R12, + Alpha::R13, Alpha::R14, + Alpha::F2, Alpha::F3, + Alpha::F4, Alpha::F5, + Alpha::F6, Alpha::F7, + Alpha::F8, Alpha::F9, 0 + }; + return CalleeSavedRegs; } -void -AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC) const { - //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; - if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); - else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); - else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); - else - abort(); +const TargetRegisterClass* const* +AlphaRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { + static const TargetRegisterClass * const CalleeSavedRegClasses[] = { + &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, + &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, + &Alpha::GPRCRegClass, &Alpha::GPRCRegClass, + &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, + &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, + &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, + &Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0 + }; + return CalleeSavedRegClasses; } -MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, - unsigned OpNum, - int FrameIndex) const { - // Make sure this is a reg-reg copy. - unsigned Opc = MI->getOpcode(); - - switch(Opc) { - default: - break; - case Alpha::BIS: - case Alpha::CPYSS: - case Alpha::CPYST: - if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { - if (OpNum == 0) { // move -> store - unsigned InReg = MI->getOperand(1).getReg(); - Opc = (Opc == Alpha::BIS) ? Alpha::STQ : - ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } else { // load -> move - unsigned OutReg = MI->getOperand(0).getReg(); - Opc = (Opc == Alpha::BIS) ? Alpha::LDQ : - ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex) - .addReg(Alpha::F31); - } - } - break; - } - return 0; -} - - -void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *RC) const { - // std::cerr << "copyRegToReg " << DestReg << " <- " << SrcReg << "\n"; - if (RC == Alpha::GPRCRegisterClass) { - BuildMI(MBB, MI, Alpha::BIS, 2, DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (RC == Alpha::F4RCRegisterClass) { - BuildMI(MBB, MI, Alpha::CPYSS, 2, DestReg).addReg(SrcReg).addReg(SrcReg); - } else if (RC == Alpha::F8RCRegisterClass) { - BuildMI(MBB, MI, Alpha::CPYST, 2, DestReg).addReg(SrcReg).addReg(SrcReg); - } else { - std::cerr << "Attempt to copy register that is not GPR or FPR"; - abort(); - } +BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { + BitVector Reserved(getNumRegs()); + Reserved.set(Alpha::R15); + Reserved.set(Alpha::R30); + Reserved.set(Alpha::R31); + return Reserved; } //===----------------------------------------------------------------------===// @@ -153,8 +104,8 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. // -static bool hasFP(MachineFunction &MF) { - MachineFrameInfo *MFI = MF.getFrameInfo(); +bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->hasVarSizedObjects(); } @@ -166,7 +117,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, // 'sub ESP, ' and the adjcallstackdown instruction into 'add ESP, // ' MachineInstr *Old = I; - uint64_t Amount = Old->getOperand(0).getImmedValue(); + uint64_t Amount = Old->getOperand(0).getImm(); if (Amount != 0) { // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next @@ -176,11 +127,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineInstr *New; if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { - New=BuildMI(Alpha::LDA, 2, Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(-Amount).addReg(Alpha::R30); } else { assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); - New=BuildMI(Alpha::LDA, 2, Alpha::R30) + New=BuildMI(MF, Old->getDebugLoc(), TII.get(Alpha::LDA), Alpha::R30) .addImm(Amount).addReg(Alpha::R30); } @@ -200,43 +151,47 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, //variable locals //<- SP -void -AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { +void AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, + int SPAdj, RegScavenger *RS) const { + assert(SPAdj == 0 && "Unexpected"); + unsigned i = 0; MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); bool FP = hasFP(MF); - while (!MI.getOperand(i).isFrameIndex()) { + while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } - int FrameIndex = MI.getOperand(i).getFrameIndex(); + int FrameIndex = MI.getOperand(i).getIndex(); // Add the base register of R30 (SP) or R15 (FP). - MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30); + MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); // Now add the frame object offset to the offset from the virtual frame index. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); - DEBUG(std::cerr << "FI: " << FrameIndex << " Offset: " << Offset << "\n"); + DOUT << "FI: " << FrameIndex << " Offset: " << Offset << "\n"; Offset += MF.getFrameInfo()->getStackSize(); - DEBUG(std::cerr << "Corrected Offset " << Offset << - " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n"); + DOUT << "Corrected Offset " << Offset + << " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n"; if (Offset > IMM_HIGH || Offset < IMM_LOW) { - DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " << Offset << "\n"); - //so in this case, we need to use a temporary register, and move the original - //inst off the SP/FP + DOUT << "Unconditionally using R28 for evil purposes Offset: " + << Offset << "\n"; + //so in this case, we need to use a temporary register, and move the + //original inst off the SP/FP //fix up the old: - MI.getOperand(i + 1).ChangeToRegister(Alpha::R28); + MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new - MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) + MachineInstr* nMI=BuildMI(MF, MI.getDebugLoc(), + TII.get(Alpha::LDAH), Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { @@ -249,35 +204,25 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); + DebugLoc dl = (MBBI != MBB.end() ? + MBBI->getDebugLoc() : DebugLoc::getUnknownLoc()); bool FP = hasFP(MF); - static int curgpdist = 0; - //handle GOP offset - BuildMI(MBB, MBBI, Alpha::LDAHg, 3, Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R27).addImm(++curgpdist); - BuildMI(MBB, MBBI, Alpha::LDAg, 3, Alpha::R29) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29) .addGlobalAddress(const_cast(MF.getFunction())) .addReg(Alpha::R29).addImm(curgpdist); //evil const_cast until MO stuff setup to handle const - BuildMI(MBB, MBBI, Alpha::ALTENT, 1) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT)) .addGlobalAddress(const_cast(MF.getFunction())); // Get the number of bytes to allocate from the FrameInfo long NumBytes = MFI->getStackSize(); - if (MFI->hasCalls() && !FP) { - // We reserve argument space for call sites in the function immediately on - // entry to the current function. This eliminates the need for add/sub - // brackets around call sites. - //If there is a frame pointer, then we don't do this - NumBytes += MFI->getMaxCallFrameSize(); - DEBUG(std::cerr << "Added " << MFI->getMaxCallFrameSize() - << " to the stack due to calls\n"); - } - if (FP) NumBytes += 8; //reserve space for the old FP @@ -293,24 +238,28 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { // adjust stack pointer: r30 -= numbytes NumBytes = -NumBytes; if (NumBytes >= IMM_LOW) { - BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) .addReg(Alpha::R30); } else if (getUpper16(NumBytes) >= IMM_LOW) { - BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30).addImm(getUpper16(NumBytes)) - .addReg(Alpha::R30); - BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(getLower16(NumBytes)) - .addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) + .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) + .addImm(getLower16(NumBytes)).addReg(Alpha::R30); } else { - std::cerr << "Too big a stack frame at " << NumBytes << "\n"; - abort(); + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Too big a stack frame at " + NumBytes; + llvm_report_error(Msg.str()); } //now if we need to, save the old FP and set the new if (FP) { - BuildMI(MBB, MBBI, Alpha::STQ, 3).addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ)) + .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); //this must be the last instr in the prolog - BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15).addReg(Alpha::R30).addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) + .addReg(Alpha::R30).addReg(Alpha::R30); } } @@ -319,8 +268,10 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); - assert(MBBI->getOpcode() == Alpha::RETDAG + assert((MBBI->getOpcode() == Alpha::RETDAG || + MBBI->getOpcode() == Alpha::RETDAGp) && "Can only insert epilog into returning blocks"); + DebugLoc dl = MBBI->getDebugLoc(); bool FP = hasFP(MF); @@ -328,34 +279,35 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, long NumBytes = MFI->getStackSize(); //now if we need to, restore the old FP - if (FP) - { + if (FP) { //copy the FP into the SP (discards allocas) - BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R30).addReg(Alpha::R15) + BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) .addReg(Alpha::R15); //restore the FP - BuildMI(MBB, MBBI, Alpha::LDQ, 2, Alpha::R15).addImm(0).addReg(Alpha::R15); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) + .addImm(0).addReg(Alpha::R15); } - if (NumBytes != 0) - { - if (NumBytes <= IMM_HIGH) { - BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30).addImm(NumBytes) - .addReg(Alpha::R30); - } else if (getUpper16(NumBytes) <= IMM_HIGH) { - BuildMI(MBB, MBBI, Alpha::LDAH, 2, Alpha::R30) - .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); - BuildMI(MBB, MBBI, Alpha::LDA, 2, Alpha::R30) - .addImm(getLower16(NumBytes)).addReg(Alpha::R30); - } else { - std::cerr << "Too big a stack frame at " << NumBytes << "\n"; - abort(); - } - } + if (NumBytes != 0) { + if (NumBytes <= IMM_HIGH) { + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) + .addReg(Alpha::R30); + } else if (getUpper16(NumBytes) <= IMM_HIGH) { + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) + .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); + BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) + .addImm(getLower16(NumBytes)).addReg(Alpha::R30); + } else { + std::string msg; + raw_string_ostream Msg(msg); + Msg << "Too big a stack frame at " + NumBytes; + llvm_report_error(Msg.str()); + } + } } unsigned AlphaRegisterInfo::getRARegister() const { - assert(0 && "What is the return address register"); + LLVM_UNREACHABLE("What is the return address register"); return 0; } @@ -363,6 +315,21 @@ unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const { return hasFP(MF) ? Alpha::R15 : Alpha::R30; } +unsigned AlphaRegisterInfo::getEHExceptionRegister() const { + LLVM_UNREACHABLE("What is the exception register"); + return 0; +} + +unsigned AlphaRegisterInfo::getEHHandlerRegister() const { + LLVM_UNREACHABLE("What is the exception handler register"); + return 0; +} + +int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { + LLVM_UNREACHABLE("What is the dwarf register number"); + return -1; +} + #include "AlphaGenRegisterInfo.inc" std::string AlphaRegisterInfo::getPrettyName(unsigned reg)