X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FTarget%2FARM%2FARMCodeEmitter.cpp;h=696547d556dc5898c043c9b7ec259d7b1454fb99;hp=1fefc0eba854368922b82b71fc755ff847ca07fb;hb=29fd056d8106c27fb0d9e4602c4d7fbd539219c6;hpb=103325179a65686d7e7dea3527d3a802b12e081e diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index 1fefc0eba85..696547d556d 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -25,6 +25,8 @@ #include "llvm/Function.h" #include "llvm/PassManager.h" #include "llvm/CodeGen/MachineCodeEmitter.h" +#include "llvm/CodeGen/JITCodeEmitter.h" +#include "llvm/CodeGen/ObjectCodeEmitter.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" @@ -33,6 +35,8 @@ #include "llvm/ADT/Statistic.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" #ifndef NDEBUG #include #endif @@ -41,23 +45,34 @@ using namespace llvm; STATISTIC(NumEmitted, "Number of machine instructions emitted"); namespace { - class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass { + + class ARMCodeEmitter { + public: + /// getBinaryCodeForInstr - This function, generated by the + /// CodeEmitterGenerator using TableGen, produces the binary encoding for + /// machine instructions. + unsigned getBinaryCodeForInstr(const MachineInstr &MI); + }; + + template + class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, + public ARMCodeEmitter { ARMJITInfo *JTI; const ARMInstrInfo *II; const TargetData *TD; TargetMachine &TM; - MachineCodeEmitter &MCE; + CodeEmitter &MCE; const std::vector *MCPEs; const std::vector *MJTEs; bool IsPIC; public: static char ID; - explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce) + explicit Emitter(TargetMachine &tm, CodeEmitter &mce) : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm), MCE(mce), MCPEs(0), MJTEs(0), IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} - ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce, + Emitter(TargetMachine &tm, CodeEmitter &mce, const ARMInstrInfo &ii, const TargetData &td) : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm), MCE(mce), MCPEs(0), MJTEs(0), @@ -75,12 +90,16 @@ namespace { void emitWordLE(unsigned Binary); + void emitDWordLE(uint64_t Binary); + void emitConstPoolInstruction(const MachineInstr &MI); void emitMOVi2piecesInstruction(const MachineInstr &MI); void emitLEApcrelJTInstruction(const MachineInstr &MI); + void emitPseudoMoveInstruction(const MachineInstr &MI); + void addPCLabel(unsigned LabelID); void emitPseudoInstruction(const MachineInstr &MI); @@ -120,11 +139,15 @@ namespace { void emitMiscBranchInstruction(const MachineInstr &MI); - /// getBinaryCodeForInstr - This function, generated by the - /// CodeEmitterGenerator using TableGen, produces the binary encoding for - /// machine instructions. - /// - unsigned getBinaryCodeForInstr(const MachineInstr &MI); + void emitVFPArithInstruction(const MachineInstr &MI); + + void emitVFPConversionInstruction(const MachineInstr &MI); + + void emitVFPLoadStoreInstruction(const MachineInstr &MI); + + void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); + + void emitMiscInstruction(const MachineInstr &MI); /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. @@ -147,17 +170,28 @@ namespace { void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, intptr_t JTBase = 0); }; - char ARMCodeEmitter::ID = 0; + template + char Emitter::ID = 0; } /// createARMCodeEmitterPass - Return a pass that emits the collected ARM code /// to the specified MCE object. -FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM, + +FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM, MachineCodeEmitter &MCE) { - return new ARMCodeEmitter(TM, MCE); + return new Emitter(TM, MCE); +} +FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, + JITCodeEmitter &JCE) { + return new Emitter(TM, JCE); +} +FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM, + ObjectCodeEmitter &OCE) { + return new Emitter(TM, OCE); } -bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { +template +bool Emitter::runOnMachineFunction(MachineFunction &MF) { assert((MF.getTarget().getRelocationModel() != Reloc::Default || MF.getTarget().getRelocationModel() != Reloc::Static) && "JIT relocation model must be set to static or default!"); @@ -167,7 +201,7 @@ bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { MCPEs = &MF.getConstantPool()->getConstants(); MJTEs = &MF.getJumpTableInfo()->getJumpTables(); IsPIC = TM.getRelocationModel() == Reloc::PIC_; - JTI->Initialize(MF); + JTI->Initialize(MF, IsPIC); do { DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n"; @@ -186,9 +220,10 @@ bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. /// -unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { +template +unsigned Emitter::getShiftOp(unsigned Imm) const { switch (ARM_AM::getAM2ShiftOpc(Imm)) { - default: assert(0 && "Unknown shift opc!"); + default: LLVM_UNREACHABLE("Unknown shift opc!"); case ARM_AM::asr: return 2; case ARM_AM::lsl: return 0; case ARM_AM::lsr: return 1; @@ -200,8 +235,9 @@ unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { /// getMachineOpValue - Return binary encoding of operand. If the machine /// operand requires relocation, record the relocation and return zero. -unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) { +template +unsigned Emitter::getMachineOpValue(const MachineInstr &MI, + const MachineOperand &MO) { if (MO.isReg()) return ARMRegisterInfo::getRegisterNumbering(MO.getReg()); else if (MO.isImm()) @@ -210,31 +246,40 @@ unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true); else if (MO.isSymbol()) emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); - else if (MO.isCPI()) - emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); - else if (MO.isJTI()) + else if (MO.isCPI()) { + const TargetInstrDesc &TID = MI.getDesc(); + // For VFP load, the immediate offset is multiplied by 4. + unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) + ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; + emitConstPoolAddress(MO.getIndex(), Reloc); + } else if (MO.isJTI()) emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); else if (MO.isMBB()) emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); else { - cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; - abort(); +#ifndef NDEBUG + cerr << MO; +#endif + llvm_unreachable(); } return 0; } /// emitGlobalAddress - Emit the specified address to the code stream. /// -void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, - bool NeedStub, intptr_t ACPV) { - MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), - Reloc, GV, ACPV, NeedStub)); +template +void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, + bool NeedStub, intptr_t ACPV) { + MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, + GV, ACPV, NeedStub)); } /// emitExternalSymbolAddress - Arrange for the address of an external symbol to /// be emitted to the current location in the function, and allow it to be PC /// relative. -void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { +template +void Emitter::emitExternalSymbolAddress(const char *ES, + unsigned Reloc) { MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), Reloc, ES)); } @@ -242,7 +287,9 @@ void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { /// emitConstPoolAddress - Arrange for the address of an constant pool /// to be emitted to the current location in the function, and allow it to be PC /// relative. -void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) { +template +void Emitter::emitConstPoolAddress(unsigned CPI, + unsigned Reloc) { // Tell JIT emitter we'll resolve the address. MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), Reloc, CPI, 0, true)); @@ -251,19 +298,23 @@ void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) { /// emitJumpTableAddress - Arrange for the address of a jump table to /// be emitted to the current location in the function, and allow it to be PC /// relative. -void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) { +template +void Emitter::emitJumpTableAddress(unsigned JTIndex, + unsigned Reloc) { MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), Reloc, JTIndex, 0, true)); } /// emitMachineBasicBlock - Emit the specified address basic block. -void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, - unsigned Reloc, intptr_t JTBase) { +template +void Emitter::emitMachineBasicBlock(MachineBasicBlock *BB, + unsigned Reloc, intptr_t JTBase) { MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), Reloc, BB, JTBase)); } -void ARMCodeEmitter::emitWordLE(unsigned Binary) { +template +void Emitter::emitWordLE(unsigned Binary) { #ifndef NDEBUG DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') << Binary << std::dec << "\n"; @@ -271,14 +322,27 @@ void ARMCodeEmitter::emitWordLE(unsigned Binary) { MCE.emitWordLE(Binary); } -void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { +template +void Emitter::emitDWordLE(uint64_t Binary) { +#ifndef NDEBUG + DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') + << (unsigned)Binary << std::dec << "\n"; + DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') + << (unsigned)(Binary >> 32) << std::dec << "\n"; +#endif + MCE.emitDWordLE(Binary); +} + +template +void Emitter::emitInstruction(const MachineInstr &MI) { DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI; NumEmitted++; // Keep track of the # of mi's emitted switch (MI.getDesc().TSFlags & ARMII::FormMask) { - default: - assert(0 && "Unhandled instruction encoding format!"); + default: { + LLVM_UNREACHABLE("Unhandled instruction encoding format!"); break; + } case ARMII::Pseudo: emitPseudoInstruction(MI); break; @@ -294,8 +358,7 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { case ARMII::StMiscFrm: emitMiscLoadStoreInstruction(MI); break; - case ARMII::LdMulFrm: - case ARMII::StMulFrm: + case ARMII::LdStMulFrm: emitLoadStoreMultipleInstruction(MI); break; case ARMII::MulFrm: @@ -313,10 +376,32 @@ void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { case ARMII::BrMiscFrm: emitMiscBranchInstruction(MI); break; + // VFP instructions. + case ARMII::VFPUnaryFrm: + case ARMII::VFPBinaryFrm: + emitVFPArithInstruction(MI); + break; + case ARMII::VFPConv1Frm: + case ARMII::VFPConv2Frm: + case ARMII::VFPConv3Frm: + case ARMII::VFPConv4Frm: + case ARMII::VFPConv5Frm: + emitVFPConversionInstruction(MI); + break; + case ARMII::VFPLdStFrm: + emitVFPLoadStoreInstruction(MI); + break; + case ARMII::VFPLdStMulFrm: + emitVFPLoadStoreMultipleInstruction(MI); + break; + case ARMII::VFPMiscFrm: + emitMiscInstruction(MI); + break; } } -void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { +template +void Emitter::emitConstPoolInstruction(const MachineInstr &MI) { unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; @@ -337,12 +422,12 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { if (GV) { assert(!ACPV->isStub() && "Don't know how to deal this yet!"); if (ACPV->isNonLazyPointer()) - MCE.addRelocation(MachineRelocation::getGVNonLazyPtr( + MCE.addRelocation(MachineRelocation::getIndirectSymbol( MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV, (intptr_t)ACPV, false)); else emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, - ACPV->isStub(), (intptr_t)ACPV); + ACPV->isStub() || isa(GV), (intptr_t)ACPV); } else { assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!"); emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); @@ -351,26 +436,42 @@ void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { } else { Constant *CV = MCPE.Val.ConstVal; +#ifndef NDEBUG DOUT << " ** Constant pool #" << CPI << " @ " - << (void*)MCE.getCurrentPCValue() << " " << *CV << '\n'; + << (void*)MCE.getCurrentPCValue() << " "; + if (const Function *F = dyn_cast(CV)) + DOUT << F->getName(); + else + DOUT << *CV; + DOUT << '\n'; +#endif if (GlobalValue *GV = dyn_cast(CV)) { - emitGlobalAddress(GV, ARM::reloc_arm_absolute, false); + emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa(GV)); emitWordLE(0); - } else { - assert(CV->getType()->isInteger() && - "Not expecting non-integer constpool entries yet!"); - const ConstantInt *CI = dyn_cast(CV); + } else if (const ConstantInt *CI = dyn_cast(CV)) { uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); emitWordLE(Val); + } else if (const ConstantFP *CFP = dyn_cast(CV)) { + if (CFP->getType() == Type::FloatTy) + emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); + else if (CFP->getType() == Type::DoubleTy) + emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); + else { + LLVM_UNREACHABLE("Unable to handle this constantpool entry!"); + } + } else { + LLVM_UNREACHABLE("Unable to handle this constantpool entry!"); } } } -void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { +template +void Emitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { const MachineOperand &MO0 = MI.getOperand(0); const MachineOperand &MO1 = MI.getOperand(1); - assert(MO1.isImm() && "Not a valid so_imm value!"); + assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 && + "Not a valid so_imm value!"); unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); @@ -386,7 +487,7 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { // Encode so_imm. // Set bit I(25) to identify this is the immediate form of Binary |= 1 << ARMII::I_BitShift; - Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1)); + Binary |= getMachineSoImmOpValue(V1); emitWordLE(Binary); // Now the 'orr' instruction. @@ -404,11 +505,12 @@ void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { // Encode so_imm. // Set bit I(25) to identify this is the immediate form of Binary |= 1 << ARMII::I_BitShift; - Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2)); + Binary |= getMachineSoImmOpValue(V2); emitWordLE(Binary); } -void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { +template +void Emitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { // It's basically add r, pc, (LJTI - $+8) const TargetInstrDesc &TID = MI.getDesc(); @@ -429,24 +531,82 @@ void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; // Encode the displacement. - // Set bit I(25) to identify this is the immediate form of . Binary |= 1 << ARMII::I_BitShift; emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); emitWordLE(Binary); } -void ARMCodeEmitter::addPCLabel(unsigned LabelID) { +template +void Emitter::emitPseudoMoveInstruction(const MachineInstr &MI) { + unsigned Opcode = MI.getDesc().Opcode; + + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + // Encode S bit if MI modifies CPSR. + if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) + Binary |= 1 << ARMII::S_BitShift; + + // Encode register def if there is one. + Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; + + // Encode the shift operation. + switch (Opcode) { + default: break; + case ARM::MOVrx: + // rrx + Binary |= 0x6 << 4; + break; + case ARM::MOVsrl_flag: + // lsr #1 + Binary |= (0x2 << 4) | (1 << 7); + break; + case ARM::MOVsra_flag: + // asr #1 + Binary |= (0x4 << 4) | (1 << 7); + break; + } + + // Encode register Rm. + Binary |= getMachineOpValue(MI, 1); + + emitWordLE(Binary); +} + +template +void Emitter::addPCLabel(unsigned LabelID) { DOUT << " ** LPC" << LabelID << " @ " << (void*)MCE.getCurrentPCValue() << '\n'; JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); } -void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { +template +void Emitter::emitPseudoInstruction(const MachineInstr &MI) { unsigned Opcode = MI.getDesc().Opcode; switch (Opcode) { default: - abort(); // FIXME: + LLVM_UNREACHABLE("ARMCodeEmitter::emitPseudoInstruction");//FIXME: + case TargetInstrInfo::INLINEASM: { + // We allow inline assembler nodes with empty bodies - they can + // implicitly define registers, which is ok for JIT. + if (MI.getOperand(0).getSymbolName()[0]) { + llvm_report_error("JIT does not support inline asm!"); + } + break; + } + case TargetInstrInfo::DBG_LABEL: + case TargetInstrInfo::EH_LABEL: + MCE.emitLabel(MI.getOperand(0).getImm()); + break; + case TargetInstrInfo::IMPLICIT_DEF: + case TargetInstrInfo::DECLARE: + case ARM::DWARF_LOC: + // Do nothing. + break; case ARM::CONSTPOOL_ENTRY: emitConstPoolInstruction(MI); break; @@ -485,11 +645,17 @@ void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { // Materialize jumptable address. emitLEApcrelJTInstruction(MI); break; + case ARM::MOVrx: + case ARM::MOVsrl_flag: + case ARM::MOVsra_flag: + emitPseudoMoveInstruction(MI); + break; } } - -unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, +template +unsigned Emitter::getMachineSoRegOpValue( + const MachineInstr &MI, const TargetInstrDesc &TID, const MachineOperand &MO, unsigned OpIdx) { @@ -510,7 +676,7 @@ unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, // ROR - 0111 // RRX - 0110 and bit[11:8] clear. switch (SOpc) { - default: assert(0 && "Unknown shift opc!"); + default: LLVM_UNREACHABLE("Unknown shift opc!"); case ARM_AM::lsl: SBits = 0x1; break; case ARM_AM::lsr: SBits = 0x3; break; case ARM_AM::asr: SBits = 0x5; break; @@ -524,7 +690,7 @@ unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, // ASR - 100 // ROR - 110 switch (SOpc) { - default: assert(0 && "Unknown shift opc!"); + default: LLVM_UNREACHABLE("Unknown shift opc!"); case ARM_AM::lsl: SBits = 0x0; break; case ARM_AM::lsr: SBits = 0x2; break; case ARM_AM::asr: SBits = 0x4; break; @@ -547,18 +713,23 @@ unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; } -unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { +template +unsigned Emitter::getMachineSoImmOpValue(unsigned SoImm) { + int SoImmVal = ARM_AM::getSOImmVal(SoImm); + assert(SoImmVal != -1 && "Not a valid so_imm value!"); + // Encode rotate_imm. - unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1) + unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) << ARMII::SoRotImmShift; // Encode immed_8. - Binary |= ARM_AM::getSOImmValImm(SoImm); + Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); return Binary; } -unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, - const TargetInstrDesc &TID) const { +template +unsigned Emitter::getAddrModeSBit(const MachineInstr &MI, + const TargetInstrDesc &TID) const { for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ const MachineOperand &MO = MI.getOperand(i-1); if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) @@ -567,11 +738,17 @@ unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, return 0; } -void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, +template +void Emitter::emitDataProcessingInstruction( + const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); + if (TID.Opcode == ARM::BFC) { + llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported."); + } + // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -623,17 +800,19 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, } // Encode so_imm. - // Set bit I(25) to identify this is the immediate form of . - Binary |= 1 << ARMII::I_BitShift; - Binary |= getMachineSoImmOpValue(MO.getImm()); + Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); emitWordLE(Binary); } -void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, +template +void Emitter::emitLoadStoreInstruction( + const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); + unsigned Form = TID.TSFlags & ARMII::FormMask; + bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -641,8 +820,17 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; - // Set first operand unsigned OpIdx = 0; + + // Operand 0 of a pre- and post-indexed store is the address base + // writeback. Skip it. + bool Skipped = false; + if (IsPrePost && Form == ARMII::StFrm) { + ++OpIdx; + Skipped = true; + } + + // Set first operand if (ImplicitRd) // Special handling for implicit use (e.g. PC). Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) @@ -659,7 +847,7 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; // If this is a two-address operand, skip it. e.g. LDR_PRE. - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) ++OpIdx; const MachineOperand &MO2 = MI.getOperand(OpIdx); @@ -683,19 +871,22 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, // Set bit[3:0] to the corresponding Rm register Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); - // if this instr is in scaled register offset/index instruction, set + // If this instr is in scaled register offset/index instruction, set // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { - Binary |= getShiftOp(AM2Opc) << 5; // shift - Binary |= ShImm << 7; // shift_immed + Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift + Binary |= ShImm << ARMII::ShiftShift; // shift_immed } emitWordLE(Binary); } -void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, - unsigned ImplicitRn) { +template +void Emitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, + unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); + unsigned Form = TID.TSFlags & ARMII::FormMask; + bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -703,11 +894,24 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; + unsigned OpIdx = 0; + + // Operand 0 of a pre- and post-indexed store is the address base + // writeback. Skip it. + bool Skipped = false; + if (IsPrePost && Form == ARMII::StMiscFrm) { + ++OpIdx; + Skipped = true; + } + // Set first operand - Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; + Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; + + // Skip LDRD and STRD's second operand. + if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) + ++OpIdx; // Set second operand - unsigned OpIdx = 1; if (ImplicitRn) // Special handling for implicit use (e.g. PC). Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) @@ -716,7 +920,7 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; // If this is a two-address operand, skip it. e.g. LDRH_POST. - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) ++OpIdx; const MachineOperand &MO2 = MI.getOperand(OpIdx); @@ -739,38 +943,48 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, Binary |= 1 << ARMII::AM3_I_BitShift; if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { // Set operands - Binary |= (ImmOffs >> 4) << 8; // immedH - Binary |= (ImmOffs & ~0xF); // immedL + Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH + Binary |= (ImmOffs & 0xF); // immedL } emitWordLE(Binary); } -void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { - // Part of binary is determined by TableGn. - unsigned Binary = getBinaryCodeForInstr(MI); - - // Set the conditional execution predicate - Binary |= II->getPredicate(&MI) << ARMII::CondShift; - - // Set first operand - Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; +static unsigned getAddrModeUPBits(unsigned Mode) { + unsigned Binary = 0; // Set addressing mode by modifying bits U(23) and P(24) // IA - Increment after - bit U = 1 and bit P = 0 // IB - Increment before - bit U = 1 and bit P = 1 // DA - Decrement after - bit U = 0 and bit P = 0 // DB - Decrement before - bit U = 0 and bit P = 1 - const MachineOperand &MO = MI.getOperand(1); - ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm()); switch (Mode) { - default: assert(0 && "Unknown addressing sub-mode!"); + default: LLVM_UNREACHABLE("Unknown addressing sub-mode!"); case ARM_AM::da: break; case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; } + return Binary; +} + +template +void Emitter::emitLoadStoreMultipleInstruction( + const MachineInstr &MI) { + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + // Set base address operand + Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; + + // Set addressing mode by modifying bits U(23) and P(24) + const MachineOperand &MO = MI.getOperand(1); + Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); + // Set bit W(21) if (ARM_AM::getAM4WBFlag(MO.getImm())) Binary |= 0x1 << ARMII::W_BitShift; @@ -778,8 +992,8 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { // Set registers for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI.getOperand(i); - if (MO.isReg() && MO.isImplicit()) - continue; + if (!MO.isReg() || MO.isImplicit()) + break; unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && RegNum < 16); @@ -789,7 +1003,8 @@ void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { emitWordLE(Binary); } -void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { +template +void Emitter::emitMulFrmInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -826,7 +1041,8 @@ void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { emitWordLE(Binary); } -void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { +template +void Emitter::emitExtendInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -863,7 +1079,8 @@ void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { emitWordLE(Binary); } -void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { +template +void Emitter::emitMiscArithInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Part of binary is determined by TableGn. @@ -901,11 +1118,13 @@ void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { emitWordLE(Binary); } -void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { +template +void Emitter::emitBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); - if (TID.Opcode == ARM::TPsoft) - abort(); // FIXME + if (TID.Opcode == ARM::TPsoft) { + LLVM_UNREACHABLE("ARM::TPsoft FIXME"); // FIXME + } // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -919,9 +1138,10 @@ void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { emitWordLE(Binary); } -void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { +template +void Emitter::emitInlineJumpTable(unsigned JTIndex) { // Remember the base address of the inline jump table. - intptr_t JTBase = MCE.getCurrentPCValue(); + uintptr_t JTBase = MCE.getCurrentPCValue(); JTI->addJumpTableBaseAddr(JTIndex, JTBase); DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n'; @@ -938,20 +1158,23 @@ void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { } } -void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { +template +void Emitter::emitMiscBranchInstruction(const MachineInstr &MI) { const TargetInstrDesc &TID = MI.getDesc(); // Handle jump tables. - if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { + if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd || + TID.Opcode == ARM::t2BR_JTr || TID.Opcode == ARM::t2BR_JTadd) { // First emit a ldr pc, [] instruction. emitDataProcessingInstruction(MI, ARM::PC); // Then emit the inline jump table. - unsigned JTIndex = (TID.Opcode == ARM::BR_JTr) + unsigned JTIndex = + (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::t2BR_JTr) ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); emitInlineJumpTable(JTIndex); return; - } else if (TID.Opcode == ARM::BR_JTm) { + } else if (TID.Opcode == ARM::BR_JTm || TID.Opcode == ARM::t2BR_JTm) { // First emit a ldr pc, [] instruction. emitLoadStoreInstruction(MI, ARM::PC); @@ -976,4 +1199,227 @@ void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { emitWordLE(Binary); } +static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { + unsigned RegD = MI.getOperand(OpIdx).getReg(); + unsigned Binary = 0; + bool isSPVFP = false; + RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP); + if (!isSPVFP) + Binary |= RegD << ARMII::RegRdShift; + else { + Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; + Binary |= (RegD & 0x01) << ARMII::D_BitShift; + } + return Binary; +} + +static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { + unsigned RegN = MI.getOperand(OpIdx).getReg(); + unsigned Binary = 0; + bool isSPVFP = false; + RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP); + if (!isSPVFP) + Binary |= RegN << ARMII::RegRnShift; + else { + Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; + Binary |= (RegN & 0x01) << ARMII::N_BitShift; + } + return Binary; +} + +static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { + unsigned RegM = MI.getOperand(OpIdx).getReg(); + unsigned Binary = 0; + bool isSPVFP = false; + RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP); + if (!isSPVFP) + Binary |= RegM; + else { + Binary |= ((RegM & 0x1E) >> 1); + Binary |= (RegM & 0x01) << ARMII::M_BitShift; + } + return Binary; +} + +template +void Emitter::emitVFPArithInstruction(const MachineInstr &MI) { + const TargetInstrDesc &TID = MI.getDesc(); + + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + unsigned OpIdx = 0; + assert((Binary & ARMII::D_BitShift) == 0 && + (Binary & ARMII::N_BitShift) == 0 && + (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); + + // Encode Dd / Sd. + Binary |= encodeVFPRd(MI, OpIdx++); + + // If this is a two-address operand, skip it, e.g. FMACD. + if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + ++OpIdx; + + // Encode Dn / Sn. + if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) + Binary |= encodeVFPRn(MI, OpIdx++); + + if (OpIdx == TID.getNumOperands() || + TID.OpInfo[OpIdx].isPredicate() || + TID.OpInfo[OpIdx].isOptionalDef()) { + // FCMPEZD etc. has only one operand. + emitWordLE(Binary); + return; + } + + // Encode Dm / Sm. + Binary |= encodeVFPRm(MI, OpIdx); + + emitWordLE(Binary); +} + +template +void Emitter::emitVFPConversionInstruction( + const MachineInstr &MI) { + const TargetInstrDesc &TID = MI.getDesc(); + unsigned Form = TID.TSFlags & ARMII::FormMask; + + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + switch (Form) { + default: break; + case ARMII::VFPConv1Frm: + case ARMII::VFPConv2Frm: + case ARMII::VFPConv3Frm: + // Encode Dd / Sd. + Binary |= encodeVFPRd(MI, 0); + break; + case ARMII::VFPConv4Frm: + // Encode Dn / Sn. + Binary |= encodeVFPRn(MI, 0); + break; + case ARMII::VFPConv5Frm: + // Encode Dm / Sm. + Binary |= encodeVFPRm(MI, 0); + break; + } + + switch (Form) { + default: break; + case ARMII::VFPConv1Frm: + // Encode Dm / Sm. + Binary |= encodeVFPRm(MI, 1); + break; + case ARMII::VFPConv2Frm: + case ARMII::VFPConv3Frm: + // Encode Dn / Sn. + Binary |= encodeVFPRn(MI, 1); + break; + case ARMII::VFPConv4Frm: + case ARMII::VFPConv5Frm: + // Encode Dd / Sd. + Binary |= encodeVFPRd(MI, 1); + break; + } + + if (Form == ARMII::VFPConv5Frm) + // Encode Dn / Sn. + Binary |= encodeVFPRn(MI, 2); + else if (Form == ARMII::VFPConv3Frm) + // Encode Dm / Sm. + Binary |= encodeVFPRm(MI, 2); + + emitWordLE(Binary); +} + +template +void Emitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + unsigned OpIdx = 0; + + // Encode Dd / Sd. + Binary |= encodeVFPRd(MI, OpIdx++); + + // Encode address base. + const MachineOperand &Base = MI.getOperand(OpIdx++); + Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; + + // If there is a non-zero immediate offset, encode it. + if (Base.isReg()) { + const MachineOperand &Offset = MI.getOperand(OpIdx); + if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { + if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) + Binary |= 1 << ARMII::U_BitShift; + Binary |= ImmOffs; + emitWordLE(Binary); + return; + } + } + + // If immediate offset is omitted, default to +0. + Binary |= 1 << ARMII::U_BitShift; + + emitWordLE(Binary); +} + +template +void Emitter::emitVFPLoadStoreMultipleInstruction( + const MachineInstr &MI) { + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + // Set base address operand + Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; + + // Set addressing mode by modifying bits U(23) and P(24) + const MachineOperand &MO = MI.getOperand(1); + Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm())); + + // Set bit W(21) + if (ARM_AM::getAM5WBFlag(MO.getImm())) + Binary |= 0x1 << ARMII::W_BitShift; + + // First register is encoded in Dd. + Binary |= encodeVFPRd(MI, 4); + + // Number of registers are encoded in offset field. + unsigned NumRegs = 1; + for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) { + const MachineOperand &MO = MI.getOperand(i); + if (!MO.isReg() || MO.isImplicit()) + break; + ++NumRegs; + } + Binary |= NumRegs * 2; + + emitWordLE(Binary); +} + +template +void Emitter::emitMiscInstruction(const MachineInstr &MI) { + // Part of binary is determined by TableGn. + unsigned Binary = getBinaryCodeForInstr(MI); + + // Set the conditional execution predicate + Binary |= II->getPredicate(&MI) << ARMII::CondShift; + + emitWordLE(Binary); +} + #include "ARMGenCodeEmitter.inc" +