X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FTarget%2FAArch64%2FAArch64TargetMachine.cpp;h=d4f19d2abd806eb7650e1c145844f3734769560e;hp=188a975d59cee5bd5b78b3ba8bc9b4b2c50c6aae;hb=8ac056b9dddd9ba35fa0c9be1dcefce9f633985f;hpb=11fcb483069abef41d89091a33cc55d747424560

diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp
index 188a975d59c..d4f19d2abd8 100644
--- a/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -270,7 +270,7 @@ bool AArch64PassConfig::addILPOpts() {
 void AArch64PassConfig::addPreRegAlloc() {
   // Use AdvSIMD scalar instructions whenever profitable.
   if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {
-    addPass(createAArch64AdvSIMDScalar(), false);
+    addPass(createAArch64AdvSIMDScalar());
     // The AdvSIMD pass may produce copies that can be rewritten to
     // be register coaleascer friendly.
     addPass(&PeepholeOptimizerID);
@@ -280,7 +280,7 @@ void AArch64PassConfig::addPreRegAlloc() {
 void AArch64PassConfig::addPostRegAlloc() {
   // Change dead register definitions to refer to the zero register.
   if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)
-    addPass(createAArch64DeadRegisterDefinitions(), false);
+    addPass(createAArch64DeadRegisterDefinitions());
   if (TM->getOptLevel() != CodeGenOpt::None &&
       (TM->getSubtarget<AArch64Subtarget>().isCortexA53() ||
        TM->getSubtarget<AArch64Subtarget>().isCortexA57()) &&
@@ -291,7 +291,7 @@ void AArch64PassConfig::addPostRegAlloc() {
 
 void AArch64PassConfig::addPreSched2() {
   // Expand some pseudo instructions to allow proper scheduling.
-  addPass(createAArch64ExpandPseudoPass(), false);
+  addPass(createAArch64ExpandPseudoPass());
   // Use load/store pair instructions when possible.
   if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)
     addPass(createAArch64LoadStoreOptimizationPass());
@@ -299,10 +299,10 @@ void AArch64PassConfig::addPreSched2() {
 
 void AArch64PassConfig::addPreEmitPass() {
   if (EnableA53Fix835769)
-    addPass(createAArch64A53Fix835769(), false);
+    addPass(createAArch64A53Fix835769());
   // Relax conditional branch instructions if they're otherwise out of
   // range of their destination.
-  addPass(createAArch64BranchRelaxation(), false);
+  addPass(createAArch64BranchRelaxation());
   if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
       TM->getSubtarget<AArch64Subtarget>().isTargetMachO())
     addPass(createAArch64CollectLOHPass());