X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=lib%2FCodeGen%2FLiveVariables.cpp;h=2af8bf316e15aa4d48dbfa814dc3adcfa457e911;hp=29686558adc1395a020d6d168bebe7c9f4ef70ac;hb=44a95e06cc0bb3a2d617fe94235aee92b1951910;hpb=3ed469ccd7b028a030b550d84b7336d146f5d8fa diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp index 29686558adc..2af8bf316e1 100644 --- a/lib/CodeGen/LiveVariables.cpp +++ b/lib/CodeGen/LiveVariables.cpp @@ -32,30 +32,34 @@ #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/DepthFirstIterator.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Config/alloca.h" #include -#include using namespace llvm; +char LiveVariables::ID = 0; static RegisterPass X("livevars", "Live Variable Analysis"); void LiveVariables::VarInfo::dump() const { - std::cerr << "Register Defined by: "; + cerr << "Register Defined by: "; if (DefInst) - std::cerr << *DefInst; + cerr << *DefInst; else - std::cerr << "\n"; - std::cerr << " Alive in blocks: "; + cerr << "\n"; + cerr << " Alive in blocks: "; for (unsigned i = 0, e = AliveBlocks.size(); i != e; ++i) - if (AliveBlocks[i]) std::cerr << i << ", "; - std::cerr << "\n Killed by:"; + if (AliveBlocks[i]) cerr << i << ", "; + cerr << " Used in blocks: "; + for (unsigned i = 0, e = UsedBlocks.size(); i != e; ++i) + if (UsedBlocks[i]) cerr << i << ", "; + cerr << "\n Killed by:"; if (Kills.empty()) - std::cerr << " No instructions.\n"; + cerr << " No instructions.\n"; else { for (unsigned i = 0, e = Kills.size(); i != e; ++i) - std::cerr << "\n #" << i << ": " << *Kills[i]; - std::cerr << "\n"; + cerr << "\n #" << i << ": " << *Kills[i]; + cerr << "\n"; } } @@ -69,31 +73,52 @@ LiveVariables::VarInfo &LiveVariables::getVarInfo(unsigned RegIdx) { else VirtRegInfo.resize(2*VirtRegInfo.size()); } - return VirtRegInfo[RegIdx]; + VarInfo &VI = VirtRegInfo[RegIdx]; + VI.AliveBlocks.resize(MF->getNumBlockIDs()); + VI.UsedBlocks.resize(MF->getNumBlockIDs()); + return VI; } bool LiveVariables::KillsRegister(MachineInstr *MI, unsigned Reg) const { - std::map >::const_iterator I = - RegistersKilled.find(MI); - if (I == RegistersKilled.end()) return false; - - // Do a binary search, as these lists can grow pretty big, particularly for - // call instructions on targets with lots of call-clobbered registers. - return std::binary_search(I->second.begin(), I->second.end(), Reg); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isRegister() && MO.isKill()) { + if ((MO.getReg() == Reg) || + (MRegisterInfo::isPhysicalRegister(MO.getReg()) && + MRegisterInfo::isPhysicalRegister(Reg) && + RegInfo->isSubRegister(MO.getReg(), Reg))) + return true; + } + } + return false; } bool LiveVariables::RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const { - std::map >::const_iterator I = - RegistersDead.find(MI); - if (I == RegistersDead.end()) return false; - - // Do a binary search, as these lists can grow pretty big, particularly for - // call instructions on targets with lots of call-clobbered registers. - return std::binary_search(I->second.begin(), I->second.end(), Reg); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isRegister() && MO.isDead()) { + if ((MO.getReg() == Reg) || + (MRegisterInfo::isPhysicalRegister(MO.getReg()) && + MRegisterInfo::isPhysicalRegister(Reg) && + RegInfo->isSubRegister(MO.getReg(), Reg))) + return true; + } + } + return false; +} + +bool LiveVariables::ModifiesRegister(MachineInstr *MI, unsigned Reg) const { + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isRegister() && MO.isDef() && MO.getReg() == Reg) + return true; + } + return false; } void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, - MachineBasicBlock *MBB) { + MachineBasicBlock *MBB, + std::vector &WorkList) { unsigned BBNum = MBB->getNumber(); // Check to see if this basic block is one of the killing blocks. If so, @@ -106,24 +131,38 @@ void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, if (MBB == VRInfo.DefInst->getParent()) return; // Terminate recursion - if (VRInfo.AliveBlocks.size() <= BBNum) - VRInfo.AliveBlocks.resize(BBNum+1); // Make space... - if (VRInfo.AliveBlocks[BBNum]) return; // We already know the block is live // Mark the variable known alive in this bb VRInfo.AliveBlocks[BBNum] = true; - for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), - E = MBB->pred_end(); PI != E; ++PI) - MarkVirtRegAliveInBlock(VRInfo, *PI); + for (MachineBasicBlock::const_pred_reverse_iterator PI = MBB->pred_rbegin(), + E = MBB->pred_rend(); PI != E; ++PI) + WorkList.push_back(*PI); } +void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo, + MachineBasicBlock *MBB) { + std::vector WorkList; + MarkVirtRegAliveInBlock(VRInfo, MBB, WorkList); + while (!WorkList.empty()) { + MachineBasicBlock *Pred = WorkList.back(); + WorkList.pop_back(); + MarkVirtRegAliveInBlock(VRInfo, Pred, WorkList); + } +} + + void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, MachineInstr *MI) { assert(VRInfo.DefInst && "Register use before def!"); + unsigned BBNum = MBB->getNumber(); + + VRInfo.UsedBlocks[BBNum] = true; + VRInfo.NumUses++; + // Check to see if this basic block is already a kill block... if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) { // Yes, this register is killed in this basic block already. Increase the @@ -141,7 +180,11 @@ void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, "Should have kill for defblock!"); // Add a new kill entry for this basic block. - VRInfo.Kills.push_back(MI); + // If this virtual register is already marked as alive in this basic block, + // that means it is alive in at least one of the successor block, it's not + // a kill. + if (!VRInfo.AliveBlocks[BBNum]) + VRInfo.Kills.push_back(MI); // Update all dominating blocks to mark them known live. for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(), @@ -149,86 +192,281 @@ void LiveVariables::HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB, MarkVirtRegAliveInBlock(VRInfo, *PI); } +bool LiveVariables::addRegisterKilled(unsigned IncomingReg, MachineInstr *MI, + bool AddIfNotFound) { + bool Found = false; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isRegister() && MO.isUse()) { + unsigned Reg = MO.getReg(); + if (!Reg) + continue; + if (Reg == IncomingReg) { + MO.setIsKill(); + Found = true; + break; + } else if (MRegisterInfo::isPhysicalRegister(Reg) && + MRegisterInfo::isPhysicalRegister(IncomingReg) && + RegInfo->isSuperRegister(IncomingReg, Reg) && + MO.isKill()) + // A super-register kill already exists. + Found = true; + } + } + + // If not found, this means an alias of one of the operand is killed. Add a + // new implicit operand if required. + if (!Found && AddIfNotFound) { + MI->addRegOperand(IncomingReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); + return true; + } + return Found; +} + +bool LiveVariables::addRegisterDead(unsigned IncomingReg, MachineInstr *MI, + bool AddIfNotFound) { + bool Found = false; + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isRegister() && MO.isDef()) { + unsigned Reg = MO.getReg(); + if (!Reg) + continue; + if (Reg == IncomingReg) { + MO.setIsDead(); + Found = true; + break; + } else if (MRegisterInfo::isPhysicalRegister(Reg) && + MRegisterInfo::isPhysicalRegister(IncomingReg) && + RegInfo->isSuperRegister(IncomingReg, Reg) && + MO.isDead()) + // There exists a super-register that's marked dead. + return true; + } + } + + // If not found, this means an alias of one of the operand is dead. Add a + // new implicit operand. + if (!Found && AddIfNotFound) { + MI->addRegOperand(IncomingReg, true/*IsDef*/,true/*IsImp*/,false/*IsKill*/, + true/*IsDead*/); + return true; + } + return Found; +} + void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { + // Turn previous partial def's into read/mod/write. + for (unsigned i = 0, e = PhysRegPartDef[Reg].size(); i != e; ++i) { + MachineInstr *Def = PhysRegPartDef[Reg][i]; + // First one is just a def. This means the use is reading some undef bits. + if (i != 0) + Def->addRegOperand(Reg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); + Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/); + } + PhysRegPartDef[Reg].clear(); + + // There was an earlier def of a super-register. Add implicit def to that MI. + // A: EAX = ... + // B: = AX + // Add implicit def to A. + if (PhysRegInfo[Reg] && PhysRegInfo[Reg] != PhysRegPartUse[Reg] && + !PhysRegUsed[Reg]) { + MachineInstr *Def = PhysRegInfo[Reg]; + if (!Def->findRegisterDefOperand(Reg)) + Def->addRegOperand(Reg, true/*IsDef*/,true/*IsImp*/); + } + + // There is a now a proper use, forget about the last partial use. + PhysRegPartUse[Reg] = NULL; PhysRegInfo[Reg] = MI; PhysRegUsed[Reg] = true; - for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); - unsigned Alias = *AliasSet; ++AliasSet) { - PhysRegInfo[Alias] = MI; - PhysRegUsed[Alias] = true; + for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) { + PhysRegInfo[SubReg] = MI; + PhysRegUsed[SubReg] = true; + } + + for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); + unsigned SuperReg = *SuperRegs; ++SuperRegs) { + // Remember the partial use of this superreg if it was previously defined. + bool HasPrevDef = PhysRegInfo[SuperReg] != NULL; + if (!HasPrevDef) { + for (const unsigned *SSRegs = RegInfo->getSuperRegisters(SuperReg); + unsigned SSReg = *SSRegs; ++SSRegs) { + if (PhysRegInfo[SSReg] != NULL) { + HasPrevDef = true; + break; + } + } + } + if (HasPrevDef) { + PhysRegInfo[SuperReg] = MI; + PhysRegPartUse[SuperReg] = MI; + } + } +} + +bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI, + SmallSet &SubKills) { + for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) { + MachineInstr *LastRef = PhysRegInfo[SubReg]; + if (LastRef != RefMI || + !HandlePhysRegKill(SubReg, RefMI, SubKills)) + SubKills.insert(SubReg); + } + + if (*RegInfo->getImmediateSubRegisters(Reg) == 0) { + // No sub-registers, just check if reg is killed by RefMI. + if (PhysRegInfo[Reg] == RefMI) + return true; + } else if (SubKills.empty()) + // None of the sub-registers are killed elsewhere... + return true; + return false; +} + +void LiveVariables::addRegisterKills(unsigned Reg, MachineInstr *MI, + SmallSet &SubKills) { + if (SubKills.count(Reg) == 0) + addRegisterKilled(Reg, MI, true); + else { + for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) + addRegisterKills(SubReg, MI, SubKills); + } +} + +bool LiveVariables::HandlePhysRegKill(unsigned Reg, MachineInstr *RefMI) { + SmallSet SubKills; + if (HandlePhysRegKill(Reg, RefMI, SubKills)) { + addRegisterKilled(Reg, RefMI, true); + return true; + } else { + // Some sub-registers are killed by another MI. + for (const unsigned *SubRegs = RegInfo->getImmediateSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) + addRegisterKills(SubReg, RefMI, SubKills); + return false; } } void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) { // Does this kill a previous version of this register? - if (MachineInstr *LastUse = PhysRegInfo[Reg]) { - if (PhysRegUsed[Reg]) - RegistersKilled[LastUse].push_back(Reg); - else - RegistersDead[LastUse].push_back(Reg); + if (MachineInstr *LastRef = PhysRegInfo[Reg]) { + if (PhysRegUsed[Reg]) { + if (!HandlePhysRegKill(Reg, LastRef)) { + if (PhysRegPartUse[Reg]) + addRegisterKilled(Reg, PhysRegPartUse[Reg], true); + } + } else if (PhysRegPartUse[Reg]) + // Add implicit use / kill to last partial use. + addRegisterKilled(Reg, PhysRegPartUse[Reg], true); + else if (LastRef != MI) + // Defined, but not used. However, watch out for cases where a super-reg + // is also defined on the same MI. + addRegisterDead(Reg, LastRef); } - PhysRegInfo[Reg] = MI; - PhysRegUsed[Reg] = false; - for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg); - unsigned Alias = *AliasSet; ++AliasSet) { - if (MachineInstr *LastUse = PhysRegInfo[Alias]) { - if (PhysRegUsed[Alias]) - RegistersKilled[LastUse].push_back(Alias); - else - RegistersDead[LastUse].push_back(Alias); + for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) { + if (MachineInstr *LastRef = PhysRegInfo[SubReg]) { + if (PhysRegUsed[SubReg]) { + if (!HandlePhysRegKill(SubReg, LastRef)) { + if (PhysRegPartUse[SubReg]) + addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true); + } + } else if (PhysRegPartUse[SubReg]) + // Add implicit use / kill to last use of a sub-register. + addRegisterKilled(SubReg, PhysRegPartUse[SubReg], true); + else if (LastRef != MI) + // This must be a def of the subreg on the same MI. + addRegisterDead(SubReg, LastRef); + } + } + + if (MI) { + for (const unsigned *SuperRegs = RegInfo->getSuperRegisters(Reg); + unsigned SuperReg = *SuperRegs; ++SuperRegs) { + if (PhysRegInfo[SuperReg] && PhysRegInfo[SuperReg] != MI) { + // The larger register is previously defined. Now a smaller part is + // being re-defined. Treat it as read/mod/write. + // EAX = + // AX = EAX, EAX + MI->addRegOperand(SuperReg, false/*IsDef*/,true/*IsImp*/,true/*IsKill*/); + MI->addRegOperand(SuperReg, true/*IsDef*/,true/*IsImp*/); + PhysRegInfo[SuperReg] = MI; + PhysRegUsed[SuperReg] = false; + PhysRegPartUse[SuperReg] = NULL; + } else { + // Remember this partial def. + PhysRegPartDef[SuperReg].push_back(MI); + } + } + + PhysRegInfo[Reg] = MI; + PhysRegUsed[Reg] = false; + PhysRegPartDef[Reg].clear(); + PhysRegPartUse[Reg] = NULL; + for (const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + unsigned SubReg = *SubRegs; ++SubRegs) { + PhysRegInfo[SubReg] = MI; + PhysRegUsed[SubReg] = false; + PhysRegPartDef[SubReg].clear(); + PhysRegPartUse[SubReg] = NULL; } - PhysRegInfo[Alias] = MI; - PhysRegUsed[Alias] = false; } } -bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - RegInfo = MF.getTarget().getRegisterInfo(); +bool LiveVariables::runOnMachineFunction(MachineFunction &mf) { + MF = &mf; + const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + RegInfo = MF->getTarget().getRegisterInfo(); assert(RegInfo && "Target doesn't have register information?"); - AllocatablePhysicalRegisters = RegInfo->getAllocatableSet(MF); + ReservedRegisters = RegInfo->getReservedRegs(mf); - // PhysRegInfo - Keep track of which instruction was the last use of a - // physical register. This is a purely local property, because all physical - // register references as presumed dead across basic blocks. - // - PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) * - RegInfo->getNumRegs()); - PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs()); - std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0); + unsigned NumRegs = RegInfo->getNumRegs(); + PhysRegInfo = new MachineInstr*[NumRegs]; + PhysRegUsed = new bool[NumRegs]; + PhysRegPartUse = new MachineInstr*[NumRegs]; + PhysRegPartDef = new SmallVector[NumRegs]; + PHIVarInfo = new SmallVector[MF->getNumBlockIDs()]; + std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0); + std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false); + std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0); /// Get some space for a respectable number of registers... VirtRegInfo.resize(64); - // Mark live-in registers as live-in. - for (MachineFunction::livein_iterator I = MF.livein_begin(), - E = MF.livein_end(); I != E; ++I) { - assert(MRegisterInfo::isPhysicalRegister(I->first) && - "Cannot have a live-in virtual register!"); - HandlePhysRegDef(I->first, 0); - } - - analyzePHINodes(MF); + analyzePHINodes(mf); // Calculate live variable information in depth first order on the CFG of the // function. This guarantees that we will see the definition of a virtual // register before its uses due to dominance properties of SSA (except for PHI // nodes, which are treated as a special case). // - MachineBasicBlock *Entry = MF.begin(); - std::set Visited; - for (df_ext_iterator DFI = df_ext_begin(Entry, Visited), - E = df_ext_end(Entry, Visited); DFI != E; ++DFI) { + MachineBasicBlock *Entry = MF->begin(); + SmallPtrSet Visited; + for (df_ext_iterator > + DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); + DFI != E; ++DFI) { MachineBasicBlock *MBB = *DFI; + // Mark live-in registers as live-in. + for (MachineBasicBlock::const_livein_iterator II = MBB->livein_begin(), + EE = MBB->livein_end(); II != EE; ++II) { + assert(MRegisterInfo::isPhysicalRegister(*II) && + "Cannot have a live-in virtual register!"); + HandlePhysRegDef(*II, 0); + } + // Loop over all of the instructions, processing them. for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) { MachineInstr *MI = I; - const TargetInstrDescriptor &MID = TII.get(MI->getOpcode()); // Process all of the operands of the instruction... unsigned NumOperandsToProcess = MI->getNumOperands(); @@ -238,34 +476,20 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { if (MI->getOpcode() == TargetInstrInfo::PHI) NumOperandsToProcess = 1; - // Loop over implicit uses, using them. - if (MID.ImplicitUses) { - for (const unsigned *ImplicitUses = MID.ImplicitUses; - *ImplicitUses; ++ImplicitUses) - HandlePhysRegUse(*ImplicitUses, MI); - } - - // Process all explicit uses... + // Process all uses... for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isUse() && MO.getReg()) { if (MRegisterInfo::isVirtualRegister(MO.getReg())){ HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI); } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && - AllocatablePhysicalRegisters[MO.getReg()]) { + !ReservedRegisters[MO.getReg()]) { HandlePhysRegUse(MO.getReg(), MI); } } } - // Loop over implicit defs, defining them. - if (MID.ImplicitDefs) { - for (const unsigned *ImplicitDefs = MID.ImplicitDefs; - *ImplicitDefs; ++ImplicitDefs) - HandlePhysRegDef(*ImplicitDefs, MI); - } - - // Process all explicit defs... + // Process all defs... for (unsigned i = 0; i != NumOperandsToProcess; ++i) { MachineOperand &MO = MI->getOperand(i); if (MO.isRegister() && MO.isDef() && MO.getReg()) { @@ -277,7 +501,7 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { // Defaults to dead VRInfo.Kills.push_back(MI); } else if (MRegisterInfo::isPhysicalRegister(MO.getReg()) && - AllocatablePhysicalRegisters[MO.getReg()]) { + !ReservedRegisters[MO.getReg()]) { HandlePhysRegDef(MO.getReg(), MI); } } @@ -288,10 +512,10 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { // bottom of this basic block. We check all of our successor blocks to see // if they have PHI nodes, and if so, we simulate an assignment at the end // of the current block. - if (!PHIVarInfo[MBB].empty()) { - std::vector& VarInfoVec = PHIVarInfo[MBB]; + if (!PHIVarInfo[MBB->getNumber()].empty()) { + SmallVector& VarInfoVec = PHIVarInfo[MBB->getNumber()]; - for (std::vector::iterator I = VarInfoVec.begin(), + for (SmallVector::iterator I = VarInfoVec.begin(), E = VarInfoVec.end(); I != E; ++I) { VarInfo& VRInfo = getVarInfo(*I); assert(VRInfo.DefInst && "Register use before def (or no def)!"); @@ -301,58 +525,62 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { } } - // Finally, if the last block in the function is a return, make sure to mark + // Finally, if the last instruction in the block is a return, make sure to mark // it as using all of the live-out values in the function. if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) { MachineInstr *Ret = &MBB->back(); - for (MachineFunction::liveout_iterator I = MF.liveout_begin(), - E = MF.liveout_end(); I != E; ++I) { + for (MachineFunction::liveout_iterator I = MF->liveout_begin(), + E = MF->liveout_end(); I != E; ++I) { assert(MRegisterInfo::isPhysicalRegister(*I) && "Cannot have a live-in virtual register!"); HandlePhysRegUse(*I, Ret); + // Add live-out registers as implicit uses. + if (Ret->findRegisterUseOperandIdx(*I) == -1) + Ret->addRegOperand(*I, false, true); } } // Loop over PhysRegInfo, killing any registers that are available at the // end of the basic block. This also resets the PhysRegInfo map. - for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i) + for (unsigned i = 0; i != NumRegs; ++i) if (PhysRegInfo[i]) HandlePhysRegDef(i, 0); + + // Clear some states between BB's. These are purely local information. + for (unsigned i = 0; i != NumRegs; ++i) + PhysRegPartDef[i].clear(); + std::fill(PhysRegInfo, PhysRegInfo + NumRegs, (MachineInstr*)0); + std::fill(PhysRegUsed, PhysRegUsed + NumRegs, false); + std::fill(PhysRegPartUse, PhysRegPartUse + NumRegs, (MachineInstr*)0); } - // Convert the information we have gathered into VirtRegInfo and transform it - // into a form usable by RegistersKilled. + // Convert and transfer the dead / killed information we have gathered into + // VirtRegInfo onto MI's. // - for (unsigned i = 0, e = VirtRegInfo.size(); i != e; ++i) - for (unsigned j = 0, e = VirtRegInfo[i].Kills.size(); j != e; ++j) { + for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) + for (unsigned j = 0, e2 = VirtRegInfo[i].Kills.size(); j != e2; ++j) { if (VirtRegInfo[i].Kills[j] == VirtRegInfo[i].DefInst) - RegistersDead[VirtRegInfo[i].Kills[j]].push_back( - i + MRegisterInfo::FirstVirtualRegister); - + addRegisterDead(i + MRegisterInfo::FirstVirtualRegister, + VirtRegInfo[i].Kills[j]); else - RegistersKilled[VirtRegInfo[i].Kills[j]].push_back( - i + MRegisterInfo::FirstVirtualRegister); + addRegisterKilled(i + MRegisterInfo::FirstVirtualRegister, + VirtRegInfo[i].Kills[j]); } - // Walk through the RegistersKilled/Dead sets, and sort the registers killed - // or dead. This allows us to use efficient binary search for membership - // testing. - for (std::map >::iterator - I = RegistersKilled.begin(), E = RegistersKilled.end(); I != E; ++I) - std::sort(I->second.begin(), I->second.end()); - for (std::map >::iterator - I = RegistersDead.begin(), E = RegistersDead.end(); I != E; ++I) - std::sort(I->second.begin(), I->second.end()); - // Check to make sure there are no unreachable blocks in the MC CFG for the // function. If so, it is due to a bug in the instruction selector or some // other part of the code generator if this happens. #ifndef NDEBUG - for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i) + for(MachineFunction::iterator i = MF->begin(), e = MF->end(); i != e; ++i) assert(Visited.count(&*i) != 0 && "unreachable basic block found"); #endif - PHIVarInfo.clear(); + delete[] PhysRegInfo; + delete[] PhysRegUsed; + delete[] PhysRegPartUse; + delete[] PhysRegPartDef; + delete[] PHIVarInfo; + return false; } @@ -362,8 +590,8 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) { /// the records for NewMI. void LiveVariables::instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI) { - // If the instruction defines any virtual registers, update the VarInfo for - // the instruction. + // If the instruction defines any virtual registers, update the VarInfo, + // kill and dead information for the instruction. for (unsigned i = 0, e = OldMI->getNumOperands(); i != e; ++i) { MachineOperand &MO = OldMI->getOperand(i); if (MO.isRegister() && MO.getReg() && @@ -371,74 +599,55 @@ void LiveVariables::instructionChanged(MachineInstr *OldMI, unsigned Reg = MO.getReg(); VarInfo &VI = getVarInfo(Reg); if (MO.isDef()) { + if (MO.isDead()) { + MO.unsetIsDead(); + addVirtualRegisterDead(Reg, NewMI); + } // Update the defining instruction. if (VI.DefInst == OldMI) VI.DefInst = NewMI; } - if (MO.isUse()) { - // If this is a kill of the value, update the VI kills list. - if (VI.removeKill(OldMI)) - VI.Kills.push_back(NewMI); // Yes, there was a kill of it + if (MO.isKill()) { + MO.unsetIsKill(); + addVirtualRegisterKilled(Reg, NewMI); } + // If this is a kill of the value, update the VI kills list. + if (VI.removeKill(OldMI)) + VI.Kills.push_back(NewMI); // Yes, there was a kill of it } } - - // Move the killed information over... - killed_iterator I, E; - tie(I, E) = killed_range(OldMI); - if (I != E) { - std::vector &V = RegistersKilled[NewMI]; - bool WasEmpty = V.empty(); - V.insert(V.end(), I, E); - if (!WasEmpty) - std::sort(V.begin(), V.end()); // Keep the reg list sorted. - RegistersKilled.erase(OldMI); - } - - // Move the dead information over... - tie(I, E) = dead_range(OldMI); - if (I != E) { - std::vector &V = RegistersDead[NewMI]; - bool WasEmpty = V.empty(); - V.insert(V.end(), I, E); - if (!WasEmpty) - std::sort(V.begin(), V.end()); // Keep the reg list sorted. - RegistersDead.erase(OldMI); - } } /// removeVirtualRegistersKilled - Remove all killed info for the specified /// instruction. void LiveVariables::removeVirtualRegistersKilled(MachineInstr *MI) { - std::map >::iterator I = - RegistersKilled.find(MI); - if (I == RegistersKilled.end()) return; - - std::vector &Regs = I->second; - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - if (MRegisterInfo::isVirtualRegister(Regs[i])) { - bool removed = getVarInfo(Regs[i]).removeKill(MI); - assert(removed && "kill not in register's VarInfo?"); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isRegister() && MO.isKill()) { + MO.unsetIsKill(); + unsigned Reg = MO.getReg(); + if (MRegisterInfo::isVirtualRegister(Reg)) { + bool removed = getVarInfo(Reg).removeKill(MI); + assert(removed && "kill not in register's VarInfo?"); + } } } - RegistersKilled.erase(I); } /// removeVirtualRegistersDead - Remove all of the dead registers for the /// specified instruction from the live variable information. void LiveVariables::removeVirtualRegistersDead(MachineInstr *MI) { - std::map >::iterator I = - RegistersDead.find(MI); - if (I == RegistersDead.end()) return; - - std::vector &Regs = I->second; - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - if (MRegisterInfo::isVirtualRegister(Regs[i])) { - bool removed = getVarInfo(Regs[i]).removeKill(MI); - assert(removed && "kill not in register's VarInfo?"); + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &MO = MI->getOperand(i); + if (MO.isRegister() && MO.isDead()) { + MO.unsetIsDead(); + unsigned Reg = MO.getReg(); + if (MRegisterInfo::isVirtualRegister(Reg)) { + bool removed = getVarInfo(Reg).removeKill(MI); + assert(removed && "kill not in register's VarInfo?"); + } } } - RegistersDead.erase(I); } /// analyzePHINodes - Gather information about the PHI nodes in here. In @@ -452,6 +661,6 @@ void LiveVariables::analyzePHINodes(const MachineFunction& Fn) { for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end(); BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI) for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2) - PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()]. + PHIVarInfo[BBI->getOperand(i + 1).getMachineBasicBlock()->getNumber()]. push_back(BBI->getOperand(i).getReg()); }