X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=include%2Fllvm%2FCodeGen%2FMachineInstr.h;h=3e76ea9c31dd7f5e082962855a7338b1d9441686;hp=89521e8fdb9847b7c8c5951f9eb7841752dc67c5;hb=5666fc71f0e2ed2c0400d8bca079a1dd3f33fe53;hpb=b2c79f2f630ed3e7da31ff8adb3014fb0ab47412 diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index 89521e8fdb9..3e76ea9c31d 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -22,18 +22,19 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/ilist.h" #include "llvm/ADT/ilist_node.h" +#include "llvm/ADT/iterator_range.h" +#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/MachineOperand.h" +#include "llvm/IR/DebugInfo.h" +#include "llvm/IR/DebugLoc.h" #include "llvm/IR/InlineAsm.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/Support/ArrayRecycler.h" -#include "llvm/Support/DebugLoc.h" #include "llvm/Target/TargetOpcodes.h" -#include namespace llvm { template class SmallVectorImpl; -class AliasAnalysis; class TargetInstrInfo; class TargetRegisterClass; class TargetRegisterInfo; @@ -41,13 +42,14 @@ class MachineFunction; class MachineMemOperand; //===----------------------------------------------------------------------===// -/// MachineInstr - Representation of each machine instruction. +/// Representation of each machine instruction. /// /// This class isn't a POD type, but it must have a trivial destructor. When a /// MachineFunction is deleted, all the contained MachineInstrs are deallocated /// without having their destructor called. /// -class MachineInstr : public ilist_node { +class MachineInstr + : public ilist_node_with_parent { public: typedef MachineMemOperand **mmo_iterator; @@ -63,10 +65,15 @@ public: NoFlags = 0, FrameSetup = 1 << 0, // Instruction is used as a part of // function frame setup code. - BundledPred = 1 << 1, // Instruction has bundled predecessors. - BundledSucc = 1 << 2 // Instruction has bundled successors. + FrameDestroy = 1 << 1, // Instruction is used as a part of + // function frame destruction code. + BundledPred = 1 << 2, // Instruction has bundled predecessors. + BundledSucc = 1 << 3 // Instruction has bundled successors. }; private: + // XXX-update: A flag that checks whether we can eliminate this instruction. + bool canEliminateMachineInstr; + const MCInstrDesc *MCID; // Instruction descriptor. MachineBasicBlock *Parent; // Pointer to the owning basic block. @@ -88,74 +95,84 @@ private: // information to AsmPrinter. uint8_t NumMemRefs; // Information on memory references. + // Note that MemRefs == nullptr, means 'don't know', not 'no memory access'. + // Calling code must treat missing information conservatively. If the number + // of memory operands required to be precise exceeds the maximum value of + // NumMemRefs - currently 256 - we remove the operands entirely. Note also + // that this is a non-owning reference to a shared copy on write buffer owned + // by the MachineFunction and created via MF.allocateMemRefsArray. mmo_iterator MemRefs; DebugLoc debugLoc; // Source line information. - MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION; - void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION; + MachineInstr(const MachineInstr&) = delete; + void operator=(const MachineInstr&) = delete; // Use MachineFunction::DeleteMachineInstr() instead. - ~MachineInstr() LLVM_DELETED_FUNCTION; + ~MachineInstr() = delete; // Intrusive list support friend struct ilist_traits; friend struct ilist_traits; void setParent(MachineBasicBlock *P) { Parent = P; } - /// MachineInstr ctor - This constructor creates a copy of the given + /// This constructor creates a copy of the given /// MachineInstr in the given MachineFunction. MachineInstr(MachineFunction &, const MachineInstr &); - /// MachineInstr ctor - This constructor create a MachineInstr and add the - /// implicit operands. It reserves space for number of operands specified by + /// This constructor create a MachineInstr and add the implicit operands. + /// It reserves space for number of operands specified by /// MCInstrDesc. An explicit DebugLoc is supplied. - MachineInstr(MachineFunction&, const MCInstrDesc &MCID, - const DebugLoc dl, bool NoImp = false); + MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl, + bool NoImp = false); // MachineInstrs are pool-allocated and owned by MachineFunction. friend class MachineFunction; public: + // XXX-update: + void disableCanEliminateMachineInstr() { + canEliminateMachineInstr = false; + } + + bool getCanEliminateMachineInstr() { + return canEliminateMachineInstr; + } + const MachineBasicBlock* getParent() const { return Parent; } MachineBasicBlock* getParent() { return Parent; } - /// getAsmPrinterFlags - Return the asm printer flags bitvector. - /// + /// Return the asm printer flags bitvector. uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; } - /// clearAsmPrinterFlags - clear the AsmPrinter bitvector - /// + /// Clear the AsmPrinter bitvector. void clearAsmPrinterFlags() { AsmPrinterFlags = 0; } - /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set. - /// + /// Return whether an AsmPrinter flag is set. bool getAsmPrinterFlag(CommentFlag Flag) const { return AsmPrinterFlags & Flag; } - /// setAsmPrinterFlag - Set a flag for the AsmPrinter. - /// + /// Set a flag for the AsmPrinter. void setAsmPrinterFlag(CommentFlag Flag) { AsmPrinterFlags |= (uint8_t)Flag; } - /// clearAsmPrinterFlag - clear specific AsmPrinter flags - /// + /// Clear specific AsmPrinter flags. void clearAsmPrinterFlag(CommentFlag Flag) { AsmPrinterFlags &= ~Flag; } - /// getFlags - Return the MI flags bitvector. + /// Return the MI flags bitvector. uint8_t getFlags() const { return Flags; } - /// getFlag - Return whether an MI flag is set. + /// Return whether an MI flag is set. bool getFlag(MIFlag Flag) const { return Flags & Flag; } - /// setFlag - Set a MI flag. + /// Set a MI flag. void setFlag(MIFlag Flag) { Flags |= (uint8_t)Flag; } @@ -171,8 +188,7 @@ public: Flags &= ~((uint8_t)Flag); } - /// isInsideBundle - Return true if MI is in a bundle (but not the first MI - /// in a bundle). + /// Return true if MI is in a bundle (but not the first MI in a bundle). /// /// A bundle looks like this before it's finalized: /// ---------------- @@ -211,7 +227,7 @@ public: return getFlag(BundledPred); } - /// isBundled - Return true if this instruction part of a bundle. This is true + /// Return true if this instruction part of a bundle. This is true /// if either itself or its following instruction is marked "InsideBundle". bool isBundled() const { return isBundledWithPred() || isBundledWithSucc(); @@ -239,12 +255,25 @@ public: /// Break bundle below this instruction. void unbundleFromSucc(); - /// getDebugLoc - Returns the debug location id of this MachineInstr. - /// - DebugLoc getDebugLoc() const { return debugLoc; } + /// Returns the debug location id of this MachineInstr. + const DebugLoc &getDebugLoc() const { return debugLoc; } - /// emitError - Emit an error referring to the source location of this - /// instruction. This should only be used for inline assembly that is somehow + /// Return the debug variable referenced by + /// this DBG_VALUE instruction. + const DILocalVariable *getDebugVariable() const { + assert(isDebugValue() && "not a DBG_VALUE"); + return cast(getOperand(2).getMetadata()); + } + + /// Return the complex address expression referenced by + /// this DBG_VALUE instruction. + const DIExpression *getDebugExpression() const { + assert(isDebugValue() && "not a DBG_VALUE"); + return cast(getOperand(3).getMetadata()); + } + + /// Emit an error referring to the source location of this instruction. + /// This should only be used for inline assembly that is somehow /// impossible to compile. Other errors should have been handled much /// earlier. /// @@ -252,13 +281,11 @@ public: /// void emitError(StringRef Msg) const; - /// getDesc - Returns the target instruction descriptor of this - /// MachineInstr. + /// Returns the target instruction descriptor of this MachineInstr. const MCInstrDesc &getDesc() const { return *MCID; } - /// getOpcode - Returns the opcode of this MachineInstr. - /// - int getOpcode() const { return MCID->Opcode; } + /// Returns the opcode of this MachineInstr. + unsigned getOpcode() const { return MCID->Opcode; } /// Access to explicit operands of the instruction. /// @@ -273,8 +300,7 @@ public: return Operands[i]; } - /// getNumExplicitOperands - Returns the number of non-implicit operands. - /// + /// Returns the number of non-implicit operands. unsigned getNumExplicitOperands() const; /// iterator/begin/end - Iterate over all operands of a machine instruction. @@ -287,13 +313,70 @@ public: const_mop_iterator operands_begin() const { return Operands; } const_mop_iterator operands_end() const { return Operands + NumOperands; } + iterator_range operands() { + return make_range(operands_begin(), operands_end()); + } + iterator_range operands() const { + return make_range(operands_begin(), operands_end()); + } + iterator_range explicit_operands() { + return make_range(operands_begin(), + operands_begin() + getNumExplicitOperands()); + } + iterator_range explicit_operands() const { + return make_range(operands_begin(), + operands_begin() + getNumExplicitOperands()); + } + iterator_range implicit_operands() { + return make_range(explicit_operands().end(), operands_end()); + } + iterator_range implicit_operands() const { + return make_range(explicit_operands().end(), operands_end()); + } + /// Returns a range over all explicit operands that are register definitions. + /// Implicit definition are not included! + iterator_range defs() { + return make_range(operands_begin(), + operands_begin() + getDesc().getNumDefs()); + } + /// \copydoc defs() + iterator_range defs() const { + return make_range(operands_begin(), + operands_begin() + getDesc().getNumDefs()); + } + /// Returns a range that includes all operands that are register uses. + /// This may include unrelated operands which are not register uses. + iterator_range uses() { + return make_range(operands_begin() + getDesc().getNumDefs(), + operands_end()); + } + /// \copydoc uses() + iterator_range uses() const { + return make_range(operands_begin() + getDesc().getNumDefs(), + operands_end()); + } + + /// Returns the number of the operand iterator \p I points to. + unsigned getOperandNo(const_mop_iterator I) const { + return I - operands_begin(); + } + /// Access to memory operands of the instruction mmo_iterator memoperands_begin() const { return MemRefs; } mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; } + /// Return true if we don't have any memory operands which described the the + /// memory access done by this instruction. If this is true, calling code + /// must be conservative. bool memoperands_empty() const { return NumMemRefs == 0; } - /// hasOneMemOperand - Return true if this instruction has exactly one - /// MachineMemOperand. + iterator_range memoperands() { + return make_range(memoperands_begin(), memoperands_end()); + } + iterator_range memoperands() const { + return make_range(memoperands_begin(), memoperands_end()); + } + + /// Return true if this instruction has exactly one MachineMemOperand. bool hasOneMemOperand() const { return NumMemRefs == 1; } @@ -307,37 +390,36 @@ public: AllInBundle // Return true if all instructions in bundle have property }; - /// hasProperty - Return true if the instruction (or in the case of a bundle, + /// Return true if the instruction (or in the case of a bundle, /// the instructions inside the bundle) has the specified property. /// The first argument is the property being queried. /// The second argument indicates whether the query should look inside /// instruction bundles. bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const { - // Inline the fast path. - if (Type == IgnoreBundle || !isBundle()) + // Inline the fast path for unbundled or bundle-internal instructions. + if (Type == IgnoreBundle || !isBundled() || isBundledWithPred()) return getDesc().getFlags() & (1 << MCFlag); - // If we have a bundle, take the slow path. + // If this is the first instruction in a bundle, take the slow path. return hasPropertyInBundle(1 << MCFlag, Type); } - /// isVariadic - Return true if this instruction can have a variable number of - /// operands. In this case, the variable operands will be after the normal + /// Return true if this instruction can have a variable number of operands. + /// In this case, the variable operands will be after the normal /// operands but before the implicit definitions and uses (if any are /// present). bool isVariadic(QueryType Type = IgnoreBundle) const { return hasProperty(MCID::Variadic, Type); } - /// hasOptionalDef - Set if this instruction has an optional definition, e.g. + /// Set if this instruction has an optional definition, e.g. /// ARM instructions which can set condition code if 's' bit is set. bool hasOptionalDef(QueryType Type = IgnoreBundle) const { return hasProperty(MCID::HasOptionalDef, Type); } - /// isPseudo - Return true if this is a pseudo instruction that doesn't + /// Return true if this is a pseudo instruction that doesn't /// correspond to a real machine instruction. - /// bool isPseudo(QueryType Type = IgnoreBundle) const { return hasProperty(MCID::Pseudo, Type); } @@ -350,16 +432,15 @@ public: return hasProperty(MCID::Call, Type); } - /// isBarrier - Returns true if the specified instruction stops control flow + /// Returns true if the specified instruction stops control flow /// from executing the instruction immediately following it. Examples include /// unconditional branches and return instructions. bool isBarrier(QueryType Type = AnyInBundle) const { return hasProperty(MCID::Barrier, Type); } - /// isTerminator - Returns true if this instruction part of the terminator for - /// a basic block. Typically this is things like return and branch - /// instructions. + /// Returns true if this instruction part of the terminator for a basic block. + /// Typically this is things like return and branch instructions. /// /// Various passes use this to insert code into the bottom of a basic block, /// but before control flow occurs. @@ -367,21 +448,21 @@ public: return hasProperty(MCID::Terminator, Type); } - /// isBranch - Returns true if this is a conditional, unconditional, or - /// indirect branch. Predicates below can be used to discriminate between + /// Returns true if this is a conditional, unconditional, or indirect branch. + /// Predicates below can be used to discriminate between /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to /// get more information. bool isBranch(QueryType Type = AnyInBundle) const { return hasProperty(MCID::Branch, Type); } - /// isIndirectBranch - Return true if this is an indirect branch, such as a + /// Return true if this is an indirect branch, such as a /// branch through a register. bool isIndirectBranch(QueryType Type = AnyInBundle) const { return hasProperty(MCID::IndirectBranch, Type); } - /// isConditionalBranch - Return true if this is a branch which may fall + /// Return true if this is a branch which may fall /// through to the next instruction or may transfer control flow to some other /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more /// information about this branch. @@ -389,7 +470,7 @@ public: return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type); } - /// isUnconditionalBranch - Return true if this is a branch which always + /// Return true if this is a branch which always /// transfers control flow to some other block. The /// TargetInstrInfo::AnalyzeBranch method can be used to get more information /// about this branch. @@ -397,8 +478,8 @@ public: return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type); } - // isPredicable - Return true if this instruction has a predicate operand that - // controls execution. It may be set to 'always', or may be set to other + /// Return true if this instruction has a predicate operand that + /// controls execution. It may be set to 'always', or may be set to other /// values. There are various methods in TargetInstrInfo that can be used to /// control and modify the predicate in this instruction. bool isPredicable(QueryType Type = AllInBundle) const { @@ -407,43 +488,48 @@ public: return hasProperty(MCID::Predicable, Type); } - /// isCompare - Return true if this instruction is a comparison. + /// Return true if this instruction is a comparison. bool isCompare(QueryType Type = IgnoreBundle) const { return hasProperty(MCID::Compare, Type); } - /// isMoveImmediate - Return true if this instruction is a move immediate + /// Return true if this instruction is a move immediate /// (including conditional moves) instruction. bool isMoveImmediate(QueryType Type = IgnoreBundle) const { return hasProperty(MCID::MoveImm, Type); } - /// isBitcast - Return true if this instruction is a bitcast instruction. - /// + /// Return true if this instruction is a bitcast instruction. bool isBitcast(QueryType Type = IgnoreBundle) const { return hasProperty(MCID::Bitcast, Type); } - /// isSelect - Return true if this instruction is a select instruction. - /// + /// Return true if this instruction is a select instruction. bool isSelect(QueryType Type = IgnoreBundle) const { return hasProperty(MCID::Select, Type); } - /// isNotDuplicable - Return true if this instruction cannot be safely - /// duplicated. For example, if the instruction has a unique labels attached + /// Return true if this instruction cannot be safely duplicated. + /// For example, if the instruction has a unique labels attached /// to it, duplicating it would cause multiple definition errors. bool isNotDuplicable(QueryType Type = AnyInBundle) const { return hasProperty(MCID::NotDuplicable, Type); } - /// hasDelaySlot - Returns true if the specified instruction has a delay slot + /// Return true if this instruction is convergent. + /// Convergent instructions can not be made control-dependent on any + /// additional values. + bool isConvergent(QueryType Type = AnyInBundle) const { + return hasProperty(MCID::Convergent, Type); + } + + /// Returns true if the specified instruction has a delay slot /// which must be filled by the code generator. bool hasDelaySlot(QueryType Type = AnyInBundle) const { return hasProperty(MCID::DelaySlot, Type); } - /// canFoldAsLoad - Return true for instructions that can be folded as + /// Return true for instructions that can be folded as /// memory operands in other instructions. The most common use for this /// is instructions that are simple loads from memory that don't modify /// the loaded value in any way, but it can also be used for instructions @@ -455,11 +541,54 @@ public: return hasProperty(MCID::FoldableAsLoad, Type); } + /// \brief Return true if this instruction behaves + /// the same way as the generic REG_SEQUENCE instructions. + /// E.g., on ARM, + /// dX VMOVDRR rY, rZ + /// is equivalent to + /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. + /// + /// Note that for the optimizers to be able to take advantage of + /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be + /// override accordingly. + bool isRegSequenceLike(QueryType Type = IgnoreBundle) const { + return hasProperty(MCID::RegSequence, Type); + } + + /// \brief Return true if this instruction behaves + /// the same way as the generic EXTRACT_SUBREG instructions. + /// E.g., on ARM, + /// rX, rY VMOVRRD dZ + /// is equivalent to two EXTRACT_SUBREG: + /// rX = EXTRACT_SUBREG dZ, ssub_0 + /// rY = EXTRACT_SUBREG dZ, ssub_1 + /// + /// Note that for the optimizers to be able to take advantage of + /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be + /// override accordingly. + bool isExtractSubregLike(QueryType Type = IgnoreBundle) const { + return hasProperty(MCID::ExtractSubreg, Type); + } + + /// \brief Return true if this instruction behaves + /// the same way as the generic INSERT_SUBREG instructions. + /// E.g., on ARM, + /// dX = VSETLNi32 dY, rZ, Imm + /// is equivalent to a INSERT_SUBREG: + /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) + /// + /// Note that for the optimizers to be able to take advantage of + /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be + /// override accordingly. + bool isInsertSubregLike(QueryType Type = IgnoreBundle) const { + return hasProperty(MCID::InsertSubreg, Type); + } + //===--------------------------------------------------------------------===// // Side Effect Analysis //===--------------------------------------------------------------------===// - /// mayLoad - Return true if this instruction could possibly read memory. + /// Return true if this instruction could possibly read memory. /// Instructions with this flag set are not necessarily simple load /// instructions, they may load a value and modify it, for example. bool mayLoad(QueryType Type = AnyInBundle) const { @@ -471,8 +600,7 @@ public: return hasProperty(MCID::MayLoad, Type); } - - /// mayStore - Return true if this instruction could possibly modify memory. + /// Return true if this instruction could possibly modify memory. /// Instructions with this flag set are not necessarily simple store /// instructions, they may store a modified value based on their operands, or /// may not actually modify anything, for example. @@ -485,11 +613,16 @@ public: return hasProperty(MCID::MayStore, Type); } + /// Return true if this instruction could possibly read or modify memory. + bool mayLoadOrStore(QueryType Type = AnyInBundle) const { + return mayLoad(Type) || mayStore(Type); + } + //===--------------------------------------------------------------------===// // Flags that indicate whether an instruction can be modified by a method. //===--------------------------------------------------------------------===// - /// isCommutable - Return true if this may be a 2- or 3-address + /// Return true if this may be a 2- or 3-address /// instruction (of the form "X = op Y, Z, ..."), which produces the same /// result if Y and Z are exchanged. If this flag is set, then the /// TargetInstrInfo::commuteInstruction method may be used to hack on the @@ -503,7 +636,7 @@ public: return hasProperty(MCID::Commutable, Type); } - /// isConvertibleTo3Addr - Return true if this is a 2-address instruction + /// Return true if this is a 2-address instruction /// which can be changed into a 3-address instruction if needed. Doing this /// transformation can be profitable in the register allocator, because it /// means that the instruction can use a 2-address form if possible, but @@ -521,7 +654,7 @@ public: return hasProperty(MCID::ConvertibleTo3Addr, Type); } - /// usesCustomInsertionHook - Return true if this instruction requires + /// Return true if this instruction requires /// custom insertion support when the DAG scheduler is inserting it into a /// machine basic block. If this is true for the instruction, it basically /// means that it is a pseudo instruction used at SelectionDAG time that is @@ -533,7 +666,7 @@ public: return hasProperty(MCID::UsesCustomInserter, Type); } - /// hasPostISelHook - Return true if this instruction requires *adjustment* + /// Return true if this instruction requires *adjustment* /// after instruction selection by calling a target hook. For example, this /// can be used to fill in ARM 's' optional operand depending on whether /// the conditional flag register is used. @@ -541,8 +674,8 @@ public: return hasProperty(MCID::HasPostISelHook, Type); } - /// isRematerializable - Returns true if this instruction is a candidate for - /// remat. This flag is deprecated, please don't use it anymore. If this + /// Returns true if this instruction is a candidate for remat. + /// This flag is deprecated, please don't use it anymore. If this /// flag is set, the isReallyTriviallyReMaterializable() method is called to /// verify the instruction is really rematable. bool isRematerializable(QueryType Type = AllInBundle) const { @@ -551,19 +684,18 @@ public: return hasProperty(MCID::Rematerializable, Type); } - /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or - /// less) than a move instruction. This is useful during certain types of - /// optimizations (e.g., remat during two-address conversion or machine licm) + /// Returns true if this instruction has the same cost (or less) than a move + /// instruction. This is useful during certain types of optimizations + /// (e.g., remat during two-address conversion or machine licm) /// where we would like to remat or hoist the instruction, but not if it costs /// more than moving the instruction into the appropriate register. Note, we /// are not marking copies from and to the same register class with this flag. bool isAsCheapAsAMove(QueryType Type = AllInBundle) const { // Only returns true for a bundle if all bundled instructions are cheap. - // FIXME: This probably requires a target hook. return hasProperty(MCID::CheapAsAMove, Type); } - /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands + /// Returns true if this instruction source operands /// have special register allocation requirements that are not captured by the /// operand register classes. e.g. ARM::STRD's two source registers must be an /// even / odd pair, ARM::STM registers have to be in ascending order. @@ -573,7 +705,7 @@ public: return hasProperty(MCID::ExtraSrcRegAllocReq, Type); } - /// hasExtraDefRegAllocReq - Returns true if this instruction def operands + /// Returns true if this instruction def operands /// have special register allocation requirements that are not captured by the /// operand register classes. e.g. ARM::LDRD's two def registers must be an /// even / odd pair, ARM::LDM registers have to be in ascending order. @@ -591,7 +723,7 @@ public: IgnoreVRegDefs // Ignore virtual register definitions }; - /// isIdenticalTo - Return true if this instruction is identical to (same + /// Return true if this instruction is identical to (same /// opcode and same operands as) the specified instruction. bool isIdenticalTo(const MachineInstr *Other, MICheckType Check = CheckDefs) const; @@ -617,31 +749,46 @@ public: /// eraseFromBundle() to erase individual bundled instructions. void eraseFromParent(); + /// Unlink 'this' from the containing basic block and delete it. + /// + /// For all definitions mark their uses in DBG_VALUE nodes + /// as undefined. Otherwise like eraseFromParent(). + void eraseFromParentAndMarkDBGValuesForRemoval(); + /// Unlink 'this' form its basic block and delete it. /// /// If the instruction is part of a bundle, the other instructions in the /// bundle remain bundled. void eraseFromBundle(); - /// isLabel - Returns true if the MachineInstr represents a label. - /// - bool isLabel() const { - return getOpcode() == TargetOpcode::PROLOG_LABEL || - getOpcode() == TargetOpcode::EH_LABEL || - getOpcode() == TargetOpcode::GC_LABEL; - } - - bool isPrologLabel() const { - return getOpcode() == TargetOpcode::PROLOG_LABEL; - } bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } + + /// Returns true if the MachineInstr represents a label. + bool isLabel() const { return isEHLabel() || isGCLabel(); } + bool isCFIInstruction() const { + return getOpcode() == TargetOpcode::CFI_INSTRUCTION; + } + + // True if the instruction represents a position in the function. + bool isPosition() const { return isLabel() || isCFIInstruction(); } + bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; } + /// A DBG_VALUE is indirect iff the first operand is a register and + /// the second operand is an immediate. + bool isIndirectDebugValue() const { + return isDebugValue() + && getOperand(0).isReg() + && getOperand(1).isImm(); + } bool isPHI() const { return getOpcode() == TargetOpcode::PHI; } bool isKill() const { return getOpcode() == TargetOpcode::KILL; } bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; } + bool isMSInlineAsm() const { + return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect(); + } bool isStackAligningInlineAsm() const; InlineAsm::AsmDialect getInlineAsmDialect() const; bool isInsertSubreg() const { @@ -662,20 +809,23 @@ public: bool isFullCopy() const { return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); } + bool isExtractSubreg() const { + return getOpcode() == TargetOpcode::EXTRACT_SUBREG; + } - /// isCopyLike - Return true if the instruction behaves like a copy. + /// Return true if the instruction behaves like a copy. /// This does not include native copy instructions. bool isCopyLike() const { return isCopy() || isSubregToReg(); } - /// isIdentityCopy - Return true is the instruction is an identity copy. + /// Return true is the instruction is an identity copy. bool isIdentityCopy() const { return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && getOperand(0).getSubReg() == getOperand(1).getSubReg(); } - /// isTransient - Return true if this is a transient instruction that is + /// Return true if this is a transient instruction that is /// either very likely to be eliminated during register allocation (such as /// copy-like instructions), or if this instruction doesn't have an /// execution-time cost. @@ -691,7 +841,7 @@ public: // Pseudo-instructions that don't produce any real output. case TargetOpcode::IMPLICIT_DEF: case TargetOpcode::KILL: - case TargetOpcode::PROLOG_LABEL: + case TargetOpcode::CFI_INSTRUCTION: case TargetOpcode::EH_LABEL: case TargetOpcode::GC_LABEL: case TargetOpcode::DBG_VALUE: @@ -699,100 +849,113 @@ public: } } - /// getBundleSize - Return the number of instructions inside the MI bundle. + /// Return the number of instructions inside the MI bundle, excluding the + /// bundle header. + /// + /// This is the number of instructions that MachineBasicBlock::iterator + /// skips, 0 for unbundled instructions. unsigned getBundleSize() const; - /// readsRegister - Return true if the MachineInstr reads the specified - /// register. If TargetRegisterInfo is passed, then it also checks if there + /// Return true if the MachineInstr reads the specified register. + /// If TargetRegisterInfo is passed, then it also checks if there /// is a read of a super-register. /// This does not count partial redefines of virtual registers as reads: /// %reg1024:6 = OP. - bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { + bool readsRegister(unsigned Reg, + const TargetRegisterInfo *TRI = nullptr) const { return findRegisterUseOperandIdx(Reg, false, TRI) != -1; } - /// readsVirtualRegister - Return true if the MachineInstr reads the specified - /// virtual register. Take into account that a partial define is a + /// Return true if the MachineInstr reads the specified virtual register. + /// Take into account that a partial define is a /// read-modify-write operation. bool readsVirtualRegister(unsigned Reg) const { return readsWritesVirtualRegister(Reg).first; } - /// readsWritesVirtualRegister - Return a pair of bools (reads, writes) - /// indicating if this instruction reads or writes Reg. This also considers - /// partial defines. + /// Return a pair of bools (reads, writes) indicating if this instruction + /// reads or writes Reg. This also considers partial defines. /// If Ops is not null, all operand indices for Reg are added. std::pair readsWritesVirtualRegister(unsigned Reg, - SmallVectorImpl *Ops = 0) const; + SmallVectorImpl *Ops = nullptr) const; - /// killsRegister - Return true if the MachineInstr kills the specified - /// register. If TargetRegisterInfo is passed, then it also checks if there is + /// Return true if the MachineInstr kills the specified register. + /// If TargetRegisterInfo is passed, then it also checks if there is /// a kill of a super-register. - bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const { + bool killsRegister(unsigned Reg, + const TargetRegisterInfo *TRI = nullptr) const { return findRegisterUseOperandIdx(Reg, true, TRI) != -1; } - /// definesRegister - Return true if the MachineInstr fully defines the - /// specified register. If TargetRegisterInfo is passed, then it also checks + /// Return true if the MachineInstr fully defines the specified register. + /// If TargetRegisterInfo is passed, then it also checks /// if there is a def of a super-register. /// NOTE: It's ignoring subreg indices on virtual registers. - bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const { + bool definesRegister(unsigned Reg, + const TargetRegisterInfo *TRI = nullptr) const { return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; } - /// modifiesRegister - Return true if the MachineInstr modifies (fully define - /// or partially define) the specified register. + /// Return true if the MachineInstr modifies (fully define or partially + /// define) the specified register. /// NOTE: It's ignoring subreg indices on virtual registers. bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const { return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; } - /// registerDefIsDead - Returns true if the register is dead in this machine - /// instruction. If TargetRegisterInfo is passed, then it also checks + /// Returns true if the register is dead in this machine instruction. + /// If TargetRegisterInfo is passed, then it also checks /// if there is a dead def of a super-register. bool registerDefIsDead(unsigned Reg, - const TargetRegisterInfo *TRI = NULL) const { + const TargetRegisterInfo *TRI = nullptr) const { return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; } - /// findRegisterUseOperandIdx() - Returns the operand index that is a use of - /// the specific register or -1 if it is not found. It further tightens - /// the search criteria to a use that kills the register if isKill is true. + /// Returns the operand index that is a use of the specific register or -1 + /// if it is not found. It further tightens the search criteria to a use + /// that kills the register if isKill is true. int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false, - const TargetRegisterInfo *TRI = NULL) const; + const TargetRegisterInfo *TRI = nullptr) const; - /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns + /// Wrapper for findRegisterUseOperandIdx, it returns /// a pointer to the MachineOperand rather than an index. MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false, - const TargetRegisterInfo *TRI = NULL) { + const TargetRegisterInfo *TRI = nullptr) { int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); - return (Idx == -1) ? NULL : &getOperand(Idx); + return (Idx == -1) ? nullptr : &getOperand(Idx); } - /// findRegisterDefOperandIdx() - Returns the operand index that is a def of - /// the specified register or -1 if it is not found. If isDead is true, defs - /// that are not dead are skipped. If Overlap is true, then it also looks for - /// defs that merely overlap the specified register. If TargetRegisterInfo is - /// non-null, then it also checks if there is a def of a super-register. + const MachineOperand *findRegisterUseOperand( + unsigned Reg, bool isKill = false, + const TargetRegisterInfo *TRI = nullptr) const { + return const_cast(this)-> + findRegisterUseOperand(Reg, isKill, TRI); + } + + /// Returns the operand index that is a def of the specified register or + /// -1 if it is not found. If isDead is true, defs that are not dead are + /// skipped. If Overlap is true, then it also looks for defs that merely + /// overlap the specified register. If TargetRegisterInfo is non-null, + /// then it also checks if there is a def of a super-register. /// This may also return a register mask operand when Overlap is true. int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false, bool Overlap = false, - const TargetRegisterInfo *TRI = NULL) const; + const TargetRegisterInfo *TRI = nullptr) const; - /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns + /// Wrapper for findRegisterDefOperandIdx, it returns /// a pointer to the MachineOperand rather than an index. MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false, - const TargetRegisterInfo *TRI = NULL) { + const TargetRegisterInfo *TRI = nullptr) { int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI); - return (Idx == -1) ? NULL : &getOperand(Idx); + return (Idx == -1) ? nullptr : &getOperand(Idx); } - /// findFirstPredOperandIdx() - Find the index of the first operand in the + /// Find the index of the first operand in the /// operand list that is used to represent the predicate. It returns -1 if /// none is found. int findFirstPredOperandIdx() const; - /// findInlineAsmFlagIdx() - Find the index of the flag word operand that + /// Find the index of the flag word operand that /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if /// getOperand(OpIdx) does not belong to an inline asm operand group. /// @@ -802,13 +965,13 @@ public: /// The flag operand is an immediate that can be decoded with methods like /// InlineAsm::hasRegClassConstraint(). /// - int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const; + int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const; - /// getRegClassConstraint - Compute the static register class constraint for - /// operand OpIdx. For normal instructions, this is derived from the - /// MCInstrDesc. For inline assembly it is derived from the flag words. + /// Compute the static register class constraint for operand OpIdx. + /// For normal instructions, this is derived from the MCInstrDesc. + /// For inline assembly it is derived from the flag words. /// - /// Returns NULL if the static register classs constraint cannot be + /// Returns NULL if the static register class constraint cannot be /// determined. /// const TargetRegisterClass* @@ -816,24 +979,56 @@ public: const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const; - /// tieOperands - Add a tie between the register operands at DefIdx and - /// UseIdx. The tie will cause the register allocator to ensure that the two + /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to + /// the given \p CurRC. + /// If \p ExploreBundle is set and MI is part of a bundle, all the + /// instructions inside the bundle will be taken into account. In other words, + /// this method accumulates all the constraints of the operand of this MI and + /// the related bundle if MI is a bundle or inside a bundle. + /// + /// Returns the register class that satisfies both \p CurRC and the + /// constraints set by MI. Returns NULL if such a register class does not + /// exist. + /// + /// \pre CurRC must not be NULL. + const TargetRegisterClass *getRegClassConstraintEffectForVReg( + unsigned Reg, const TargetRegisterClass *CurRC, + const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, + bool ExploreBundle = false) const; + + /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand + /// to the given \p CurRC. + /// + /// Returns the register class that satisfies both \p CurRC and the + /// constraints set by \p OpIdx MI. Returns NULL if such a register class + /// does not exist. + /// + /// \pre CurRC must not be NULL. + /// \pre The operand at \p OpIdx must be a register. + const TargetRegisterClass * + getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, + const TargetInstrInfo *TII, + const TargetRegisterInfo *TRI) const; + + /// Add a tie between the register operands at DefIdx and UseIdx. + /// The tie will cause the register allocator to ensure that the two /// operands are assigned the same physical register. /// /// Tied operands are managed automatically for explicit operands in the /// MCInstrDesc. This method is for exceptional cases like inline asm. void tieOperands(unsigned DefIdx, unsigned UseIdx); - /// findTiedOperandIdx - Given the index of a tied register operand, find the + /// Given the index of a tied register operand, find the /// operand it is tied to. Defs are tied to uses and vice versa. Returns the /// index of the tied operand which must exist. unsigned findTiedOperandIdx(unsigned OpIdx) const; - /// isRegTiedToUseOperand - Given the index of a register def operand, + /// Given the index of a register def operand, /// check if the register def is tied to a source operand, due to either /// two-address elimination or inline assembly constraints. Returns the /// first tied use operand index by reference if UseOpIdx is not null. - bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const { + bool isRegTiedToUseOperand(unsigned DefOpIdx, + unsigned *UseOpIdx = nullptr) const { const MachineOperand &MO = getOperand(DefOpIdx); if (!MO.isReg() || !MO.isDef() || !MO.isTied()) return false; @@ -842,10 +1037,11 @@ public: return true; } - /// isRegTiedToDefOperand - Return true if the use operand of the specified - /// index is tied to an def operand. It also returns the def operand index by - /// reference if DefOpIdx is not null. - bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const { + /// Return true if the use operand of the specified index is tied to a def + /// operand. It also returns the def operand index by reference if DefOpIdx + /// is not null. + bool isRegTiedToDefOperand(unsigned UseOpIdx, + unsigned *DefOpIdx = nullptr) const { const MachineOperand &MO = getOperand(UseOpIdx); if (!MO.isReg() || !MO.isUse() || !MO.isTied()) return false; @@ -854,16 +1050,15 @@ public: return true; } - /// clearKillInfo - Clears kill flags on all operands. - /// + /// Clears kill flags on all operands. void clearKillInfo(); - /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx, + /// Replace all occurrences of FromReg with ToReg:SubIdx, /// properly composing subreg indices where necessary. void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo); - /// addRegisterKilled - We have determined MI kills a register. Look for the + /// We have determined MI kills a register. Look for the /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, /// add a implicit operand if it's not found. Returns true if the operand /// exists / is added. @@ -871,23 +1066,31 @@ public: const TargetRegisterInfo *RegInfo, bool AddIfNotFound = false); - /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is + /// Clear all kill flags affecting Reg. If RegInfo is /// provided, this includes super-register kills. void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo); - /// addRegisterDead - We have determined MI defined a register without a use. + /// We have determined MI defined a register without a use. /// Look for the operand that defines it and mark it as IsDead. If /// AddIfNotFound is true, add a implicit operand if it's not found. Returns /// true if the operand exists / is added. - bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo, + bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo, bool AddIfNotFound = false); - /// addRegisterDefined - We have determined MI defines a register. Make sure - /// there is an operand defining Reg. - void addRegisterDefined(unsigned IncomingReg, - const TargetRegisterInfo *RegInfo = 0); + /// Clear all dead flags on operands defining register @p Reg. + void clearRegisterDeads(unsigned Reg); + + /// Mark all subregister defs of register @p Reg with the undef flag. + /// This function is used when we determined to have a subregister def in an + /// otherwise undefined super register. + void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true); + + /// We have determined MI defines a register. Make sure there is an operand + /// defining Reg. + void addRegisterDefined(unsigned Reg, + const TargetRegisterInfo *RegInfo = nullptr); - /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as + /// Mark every physreg used by this instruction as /// dead except those in the UsedRegs list. /// /// On instructions with register mask operands, also add implicit-def @@ -895,37 +1098,30 @@ public: void setPhysRegsDeadExcept(ArrayRef UsedRegs, const TargetRegisterInfo &TRI); - /// isSafeToMove - Return true if it is safe to move this instruction. If + /// Return true if it is safe to move this instruction. If /// SawStore is set to true, it means that there is a store (or call) between /// the instruction's location and its intended destination. - bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA, - bool &SawStore) const; + bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const; - /// isSafeToReMat - Return true if it's safe to rematerialize the specified - /// instruction which defined the specified register instead of copying it. - bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA, - unsigned DstReg) const; - - /// hasOrderedMemoryRef - Return true if this instruction may have an ordered + /// Return true if this instruction may have an ordered /// or volatile memory reference, or if the information describing the memory /// reference is not available. Return false if it is known to have no /// ordered or volatile memory references. bool hasOrderedMemoryRef() const; - /// isInvariantLoad - Return true if this instruction is loading from a + /// Return true if this instruction is loading from a /// location whose value is invariant across the function. For example, /// loading a value from the constant pool or from the argument area of /// a function if it does not change. This should only return true of *all* /// loads the instruction does are invariant (if it does multiple loads). bool isInvariantLoad(AliasAnalysis *AA) const; - /// isConstantValuePHI - If the specified instruction is a PHI that always - /// merges together the same virtual register, return the register, otherwise - /// return 0. + /// If the specified instruction is a PHI that always merges together the + /// same virtual register, return the register, otherwise return 0. unsigned isConstantValuePHI() const; - /// hasUnmodeledSideEffects - Return true if this instruction has side - /// effects that are not modeled by mayLoad / mayStore, etc. + /// Return true if this instruction has side effects that are not modeled + /// by mayLoad / mayStore, etc. /// For all instructions, the property is encoded in MCInstrDesc::Flags /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is /// INLINEASM instruction, in which case the side effect property is encoded @@ -933,18 +1129,22 @@ public: /// bool hasUnmodeledSideEffects() const; - /// allDefsAreDead - Return true if all the defs of this instruction are dead. - /// + /// Returns true if it is illegal to fold a load across this instruction. + bool isLoadFoldBarrier() const; + + /// Return true if all the defs of this instruction are dead. bool allDefsAreDead() const; - /// copyImplicitOps - Copy implicit register operands from specified + /// Copy implicit register operands from specified /// instruction to this instruction. void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI); // // Debugging support // - void print(raw_ostream &OS, const TargetMachine *TM = 0) const; + void print(raw_ostream &OS, bool SkipOpers = false) const; + void print(raw_ostream &OS, ModuleSlotTracker &MST, + bool SkipOpers = false) const; void dump() const; //===--------------------------------------------------------------------===// @@ -969,41 +1169,59 @@ public: /// preferred. void addOperand(const MachineOperand &Op); - /// setDesc - Replace the instruction descriptor (thus opcode) of + /// Replace the instruction descriptor (thus opcode) of /// the current instruction with a new one. - /// void setDesc(const MCInstrDesc &tid) { MCID = &tid; } - /// setDebugLoc - Replace current source information with new such. + /// Replace current source information with new such. /// Avoid using this, the constructor argument is preferable. - /// - void setDebugLoc(const DebugLoc dl) { debugLoc = dl; } + void setDebugLoc(DebugLoc dl) { + debugLoc = std::move(dl); + assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor"); + } - /// RemoveOperand - Erase an operand from an instruction, leaving it with one + /// Erase an operand from an instruction, leaving it with one /// fewer operand than it started with. - /// void RemoveOperand(unsigned i); - /// addMemOperand - Add a MachineMemOperand to the machine instruction. + /// Add a MachineMemOperand to the machine instruction. /// This function should be used only occasionally. The setMemRefs function /// is the primary method for setting up a MachineInstr's MemRefs list. void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); - /// setMemRefs - Assign this MachineInstr's memory reference descriptor - /// list. This does not transfer ownership. + /// Assign this MachineInstr's memory reference descriptor list. + /// This does not transfer ownership. void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) { - MemRefs = NewMemRefs; - NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs); - assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs"); + setMemRefs(std::make_pair(NewMemRefs, NewMemRefsEnd-NewMemRefs)); } -private: - /// getRegInfo - If this instruction is embedded into a MachineFunction, - /// return the MachineRegisterInfo object for the current function, otherwise - /// return null. - MachineRegisterInfo *getRegInfo(); + /// Assign this MachineInstr's memory reference descriptor list. First + /// element in the pair is the begin iterator/pointer to the array; the + /// second is the number of MemoryOperands. This does not transfer ownership + /// of the underlying memory. + void setMemRefs(std::pair NewMemRefs) { + MemRefs = NewMemRefs.first; + NumMemRefs = uint8_t(NewMemRefs.second); + assert(NumMemRefs == NewMemRefs.second && + "Too many memrefs - must drop memory operands"); + } + + /// Return a set of memrefs (begin iterator, size) which conservatively + /// describe the memory behavior of both MachineInstrs. This is appropriate + /// for use when merging two MachineInstrs into one. This routine does not + /// modify the memrefs of the this MachineInstr. + std::pair mergeMemRefsWith(const MachineInstr& Other); + + /// Clear this MachineInstr's memory reference descriptor list. This resets + /// the memrefs to their most conservative state. This should be used only + /// as a last resort since it greatly pessimizes our knowledge of the memory + /// access performed by the instruction. + void dropMemRefs() { + MemRefs = nullptr; + NumMemRefs = 0; + } - /// untieRegOperand - Break any tie involving OpIdx. + /// Break any tie involving OpIdx. void untieRegOperand(unsigned OpIdx) { MachineOperand &MO = getOperand(OpIdx); if (MO.isReg() && MO.isTied()) { @@ -1012,32 +1230,43 @@ private: } } - /// addImplicitDefUseOperands - Add all implicit def and use operands to - /// this instruction. + /// Add all implicit def and use operands to this instruction. void addImplicitDefUseOperands(MachineFunction &MF); - /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in - /// this instruction from their respective use lists. This requires that the - /// operands already be on their use lists. +private: + /// If this instruction is embedded into a MachineFunction, return the + /// MachineRegisterInfo object for the current function, otherwise + /// return null. + MachineRegisterInfo *getRegInfo(); + + /// Unlink all of the register operands in this instruction from their + /// respective use lists. This requires that the operands already be on their + /// use lists. void RemoveRegOperandsFromUseLists(MachineRegisterInfo&); - /// AddRegOperandsToUseLists - Add all of the register operands in - /// this instruction from their respective use lists. This requires that the - /// operands not be on their use lists yet. + /// Add all of the register operands in this instruction from their + /// respective use lists. This requires that the operands not be on their + /// use lists yet. void AddRegOperandsToUseLists(MachineRegisterInfo&); - /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a - /// bundle. + /// Slow path for hasProperty when we're dealing with a bundle. bool hasPropertyInBundle(unsigned Mask, QueryType Type) const; + + /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the + /// this MI and the given operand index \p OpIdx. + /// If the related operand does not constrained Reg, this returns CurRC. + const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl( + unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC, + const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const; }; -/// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare -/// MachineInstr* by *value* of the instruction rather than by pointer value. +/// Special DenseMapInfo traits to compare MachineInstr* by *value* of the +/// instruction rather than by pointer value. /// The hashing and equality testing functions ignore definitions so this is /// useful for CSE, etc. struct MachineInstrExpressionTrait : DenseMapInfo { static inline MachineInstr *getEmptyKey() { - return 0; + return nullptr; } static inline MachineInstr *getTombstoneKey() {