X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=bindings%2Focaml%2Ftarget%2Fllvm_target.mli;fp=bindings%2Focaml%2Ftarget%2Fllvm_target.mli;h=676bc613c649c4b21c86d29f5b881ba17c246dad;hp=ca91e0d9105e009f93138ac8fd473b0ac5547017;hb=57d796af1f71ebb60386d27944b6c63b3bb02edd;hpb=2e9579037de6b05ea436abf6d4bf24d9a278942b

diff --git a/bindings/ocaml/target/llvm_target.mli b/bindings/ocaml/target/llvm_target.mli
index ca91e0d9105..676bc613c64 100644
--- a/bindings/ocaml/target/llvm_target.mli
+++ b/bindings/ocaml/target/llvm_target.mli
@@ -207,6 +207,10 @@ module TargetMachine : sig
   (** Returns the data layout of this target machine. *)
   val data_layout : t -> DataLayout.t
 
+  (** Adds the target-specific analysis passes to the pass manager.
+      See [llvm::TargetMachine::addAnalysisPasses]. *)
+  val add_analysis_passes : [< Llvm.PassManager.any ] Llvm.PassManager.t -> t -> unit
+
   (** Sets the assembly verbosity of this target machine.
       See [llvm::TargetMachine::setAsmVerbosity]. *)
   val set_verbose_asm : bool -> t -> unit