X-Git-Url: http://plrg.eecs.uci.edu/git/?p=oota-llvm.git;a=blobdiff_plain;f=CREDITS.TXT;h=40d67f4f2dce46a6d215094a8847a65a91488a14;hp=5ec33be1b0c42028cd7cccd8d566de82e38b8eb2;hb=29e82393abf3d8f578c6719af03b596858761a4f;hpb=a4a1671d8148f76cb48857a8619ef0ebfd90e6ea diff --git a/CREDITS.TXT b/CREDITS.TXT index 5ec33be1b0c..40d67f4f2dc 100644 --- a/CREDITS.TXT +++ b/CREDITS.TXT @@ -5,8 +5,8 @@ done! The list is sorted by surname and formatted to allow easy grepping and beautification by scripts. The fields are: name (N), email (E), web-address -(W), PGP key ID and fingerprint (P), description (D), and snail-mail address -(S). +(W), PGP key ID and fingerprint (P), description (D), snail-mail address +(S), and (I) IRC handle. N: Vikram Adve @@ -17,11 +17,15 @@ D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM N: Owen Anderson E: resistor@mac.com D: LCSSA pass and related LoopUnswitch work -D: GVNPRE pass, TargetData refactoring, random improvements +D: GVNPRE pass, DataLayout refactoring, random improvements N: Henrik Bach D: MingW Win32 API portability layer +N: Aaron Ballman +E: aaron@aaronballman.com +D: __declspec attributes, Windows support, general bug fixing + N: Nate Begeman E: natebegeman@mac.com D: PowerPC backend developer @@ -32,6 +36,10 @@ E: dberlin@dberlin.org D: ET-Forest implementation. D: Sparse bitmap +N: David Blaikie +E: dblaikie@gmail.com +D: General bug fixing/fit & finish, mostly in Clang + N: Neil Booth E: neil@daikokuya.co.uk D: APFloat implementation. @@ -46,9 +54,17 @@ N: Cameron Buschardt E: buschard@uiuc.edu D: The `mem2reg' pass - promotes values stored in memory to registers +N: Brendon Cahoon +E: bcahoon@codeaurora.org +D: Loop unrolling with run-time trip counts. + N: Chandler Carruth E: chandlerc@gmail.com -D: LinkTimeOptimizer for Linux, via binutils integration, and C API +E: chandlerc@google.com +D: Hashing algorithms and interfaces +D: Inline cost analysis +D: Machine block placement pass +D: SROA N: Casey Carter E: ccarter@uiuc.edu @@ -79,18 +95,34 @@ N: John T. Criswell E: criswell@uiuc.edu D: Original Autoconf support, documentation improvements, bug fixes +N: Anshuman Dasgupta +E: adasgupt@codeaurora.org +D: Deterministic finite automaton based infrastructure for VLIW packetization + N: Stefanus Du Toit -E: stefanus.dutoit@rapidmind.com +E: stefanus.du.toit@intel.com D: Bug fixes and minor improvements N: Rafael Avila de Espindola E: rafael.espindola@gmail.com D: The ARM backend +N: Dave Estes +E: cestes@codeaurora.org +D: AArch64 machine description for Cortex-A53 + N: Alkis Evlogimenos E: alkis@evlogimenos.com D: Linear scan register allocator, many codegen improvements, Java frontend +N: Hal Finkel +E: hfinkel@anl.gov +D: Basic-block autovectorization, PowerPC backend improvements + +N: Eric Fiselier +E: eric@efcs.ca +D: LIT patches and documentation. + N: Ryan Flynn E: pizza@parseerror.com D: Miscellaneous bug fixes @@ -108,6 +140,7 @@ W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/ D: PPC backend fixes for Linux N: Louis Gerbarg +E: lgg@apple.com D: Portions of the PowerPC backend N: Saem Ghani @@ -119,7 +152,7 @@ E: foldr@codedgers.com D: Author of llvmc2 N: Dan Gohman -E: gohman@apple.com +E: dan433584@gmail.com D: Miscellaneous bug fixes N: David Goodwin @@ -137,8 +170,12 @@ D: Improvements for space efficiency N: James Grosbach E: grosbach@apple.com +I: grosbach D: SjLj exception handling support D: General fixes and improvements for the ARM back-end +D: MCJIT +D: ARM integrated assembler and assembly parser +D: Led effort for the backend formerly known as ARM64 N: Lang Hames E: lhames@gmail.com @@ -196,6 +233,10 @@ N: Benjamin Kramer E: benny.kra@gmail.com D: Miscellaneous bug fixes +N: Sundeep Kushwaha +E: sundeepk@codeaurora.org +D: Implemented DFA-based target independent VLIW packetizer + N: Christopher Lamb E: christopher.lamb@gmail.com D: aligned load/store support, parts of noalias and restrict support @@ -221,6 +262,13 @@ D: The initial llvm-ar tool, converted regression testsuite to dejagnu D: Modulo scheduling in the SparcV9 backend D: Release manager (1.7+) +N: Sylvestre Ledru +E: sylvestre@debian.org +W: http://sylvestre.ledru.info/ +W: http://llvm.org/apt/ +D: Debian and Ubuntu packaging +D: Continuous integration with jenkins + N: Andrew Lenharth E: alenhar2@cs.uiuc.edu W: http://www.lenharth.org/~andrewl/ @@ -231,16 +279,27 @@ N: Nick Lewycky E: nicholas@mxc.ca D: PredicateSimplifier pass +N: Tony Linthicum, et. al. +E: tlinth@codeaurora.org +D: Backend for Qualcomm's Hexagon VLIW processor. + N: Bruno Cardoso Lopes E: bruno.cardoso@gmail.com -W: http://www.brunocardoso.org -D: The Mips backend +I: bruno +W: http://brunocardoso.cc +D: Mips backend +D: Random ARM integrated assembler and assembly parser improvements +D: General X86 AVX1 support N: Duraid Madina E: duraid@octopus.com.au W: http://kinoko.c.u-tokyo.ac.jp/~duraid/ D: IA64 backend, BigBlock register allocator +N: John McCall +E: rjmccall@apple.com +D: Clang semantic analysis and IR generation + N: Michael McCracken E: michael.mccracken@gmail.com D: Line number support for llvmgcc @@ -253,10 +312,16 @@ N: Scott Michel E: scottm@aero.org D: Added STI Cell SPU backend. +N: Kai Nacke +E: kai@redstar.de +D: Support for implicit TLS model used with MS VC runtime +D: Dumping of Win64 EH structures + N: Takumi Nakamura E: geek4civic@gmail.com E: chapuni@hf.rim.or.jp D: Cygwin and MinGW support. +D: Win32 tweaks. S: Yokohama, Japan N: Edward O'Callaghan @@ -274,6 +339,8 @@ N: Jakob Stoklund Olesen E: stoklund@2pi.dk D: Machine code verifier D: Blackfin backend +D: Fast register allocator +D: Greedy register allocator N: Richard Osborne E: richard@xmos.com @@ -285,9 +352,9 @@ D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements D: Optimizer improvements, Loop Index Split -N: Sandeep Patel -E: deeppatel1987@gmail.com -D: ARM calling conventions rewrite, hard float support +N: Ana Pazos +E: apazos@codeaurora.org +D: Fixes and improvements to the AArch64 backend N: Wesley Peck E: peckw@wesleypeck.com @@ -303,12 +370,37 @@ W: http://vladimir_prus.blogspot.com E: ghost@cs.msu.su D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass +N: Kalle Raiskila +E: kalle.rasikila@nokia.com +D: Some bugfixes to CellSPU + +N: Xerxes Ranby +E: xerxes@zafena.se +D: Cmake dependency chain and various bug fixes + +N: Alex Rosenberg +E: alexr@leftfield.org +I: arosenberg +D: ARM calling conventions rewrite, hard float support + +N: Chad Rosier +E: mcrosier@codeaurora.org +I: mcrosier +D: AArch64 fast instruction selection pass +D: Fixes and improvements to the ARM fast-isel pass +D: Fixes and improvements to the AArch64 backend + +N: Nadav Rotem +E: nrotem@apple.com +D: X86 code generation improvements, Loop Vectorizer. + N: Roman Samoilov E: roman@codedgers.com D: MSIL backend N: Duncan Sands E: baldrick@free.fr +I: baldrick D: Ada support in llvm-gcc D: Dragonegg plugin D: Exception handling improvements @@ -340,6 +432,15 @@ E: rspencer@reidspencer.com W: http://reidspencer.com/ D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid +N: Alp Toker +E: alp@nuanti.com +W: http://atoker.com/ +D: C++ frontend next generation standards implementation + +N: Craig Topper +E: craig.topper@gmail.com +D: X86 codegen and disassembler improvements. AVX2 support. + N: Edwin Torok E: edwintorok@gmail.com D: Miscellaneous bug fixes @@ -353,14 +454,13 @@ E: lauro.venancio@indt.org.br D: ARM backend improvements D: Thread Local Storage implementation -N: Xerxes Ranby -E: xerxes@zafena.se -D: Cmake dependency chain and various bug fixes - N: Bill Wendling -E: wendling@apple.com +I: wendling +E: isanbard@gmail.com +D: Release manager, IR Linker, LTO D: Bunches of stuff N: Bob Wilson E: bob.wilson@acm.org -D: Advanced SIMD (NEON) support in the ARM backend +D: Advanced SIMD (NEON) support in the ARM backend. +