#include "AsmWriterInst.h"
#include "CodeGenTarget.h"
#include "SequenceToOffsetTable.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/Debug.h"
#include <vector>
using namespace llvm;
+#define DEBUG_TYPE "asm-writer-emitter"
+
namespace {
class AsmWriterEmitter {
RecordKeeper &Records;
std::map<const CodeGenInstruction*, AsmWriterInst*> CGIAWIMap;
const std::vector<const CodeGenInstruction*> *NumberedInstructions;
std::vector<AsmWriterInst> Instructions;
+ std::vector<std::string> PrintMethods;
public:
AsmWriterEmitter(RecordKeeper &R);
for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
const AsmWriterInst *Inst = getAsmWriterInstByID(i);
- if (Inst == 0)
+ if (!Inst)
continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc.
std::string Command;
// Otherwise, scan to see if all of the other instructions in this command
// set share the operand.
bool AllSame = true;
- // Keep track of the maximum, number of operands or any
- // instruction we see in the group.
- size_t MaxSize = FirstInst->Operands.size();
for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx);
NIT != InstIdxs.end();
const AsmWriterInst *OtherInst =
getAsmWriterInstByID(NIT-InstIdxs.begin());
- if (OtherInst &&
- OtherInst->Operands.size() > FirstInst->Operands.size())
- MaxSize = std::max(MaxSize, OtherInst->Operands.size());
-
if (!OtherInst || OtherInst->Operands.size() == Op ||
OtherInst->Operands[Op] != FirstInst->Operands[Op]) {
AllSame = false;
void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) {
Record *AsmWriter = Target.getAsmWriter();
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+ unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
O <<
"/// printInstruction - This method is automatically generated by tablegen\n"
"/// from the instruction set description.\n"
"void " << Target.getName() << ClassName
- << "::printInstruction(const MCInst *MI, raw_ostream &O) {\n";
+ << "::printInstruction(const MCInst *MI, "
+ << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
+ << "raw_ostream &O) {\n";
// Build an aggregate string, and build a table of offsets into it.
SequenceToOffsetTable<std::string> StringTable;
// representation.
for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)];
- if (AWI != 0 &&
+ if (AWI &&
AWI->Operands[0].OperandType ==
AsmWriterOperand::isLiteralTextOperand &&
!AWI->Operands[0].Str.empty()) {
for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)];
unsigned Idx;
- if (AWI == 0) {
+ if (!AWI) {
// Something not handled by the asmwriter printer.
Idx = ~0U;
} else if (AWI->Operands[0].OperandType !=
// in the opcode-indexed table.
unsigned BitsLeft = 64-AsmStrBits;
- std::vector<std::vector<std::string> > TableDrivenOperandPrinters;
+ std::vector<std::vector<std::string>> TableDrivenOperandPrinters;
while (1) {
std::vector<std::string> UniqueOperandCommands;
}
// Remember the handlers for this set of operands.
- TableDrivenOperandPrinters.push_back(UniqueOperandCommands);
+ TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands));
}
}
// Emit the string itself.
- O << " const char AsmStrs[] = {\n";
+ O << " static const char AsmStrs[] = {\n";
StringTable.emit(O, printChar);
O << " };\n\n";
O << " switch ((Bits >> "
<< (64-BitsLeft) << ") & "
<< ((1 << NumBits)-1) << ") {\n"
- << " default: // unreachable.\n";
+ << " default: llvm_unreachable(\"Invalid command number.\");\n";
// Print out all the cases.
for (unsigned i = 0, e = Commands.size(); i != e; ++i) {
O << "}\n";
}
+static const char *getMinimalTypeForRange(uint64_t Range) {
+ assert(Range < 0xFFFFFFFFULL && "Enum too large");
+ if (Range > 0xFFFF)
+ return "uint32_t";
+ if (Range > 0xFF)
+ return "uint16_t";
+ return "uint8_t";
+}
+
static void
emitRegisterNameString(raw_ostream &O, StringRef AltName,
- const std::vector<CodeGenRegister*> &Registers) {
+ const std::deque<CodeGenRegister> &Registers) {
SequenceToOffsetTable<std::string> StringTable;
SmallVector<std::string, 4> AsmNames(Registers.size());
- for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
- const CodeGenRegister &Reg = *Registers[i];
- std::string &AsmName = AsmNames[i];
+ unsigned i = 0;
+ for (const auto &Reg : Registers) {
+ std::string &AsmName = AsmNames[i++];
// "NoRegAltName" is special. We don't need to do a lookup for that,
// as it's just a reference to the default register name.
Reg.TheDef->getValueAsListOfStrings("AltNames");
if (AltNames.size() <= Idx)
PrintFatalError(Reg.TheDef->getLoc(),
- (Twine("Register definition missing alt name for '") +
- AltName + "'.").str());
+ "Register definition missing alt name for '" +
+ AltName + "'.");
AsmName = AltNames[Idx];
}
}
StringTable.emit(O, printChar);
O << " };\n\n";
- O << " static const uint32_t RegAsmOffset" << AltName << "[] = {";
+ O << " static const " << getMinimalTypeForRange(StringTable.size()-1)
+ << " RegAsmOffset" << AltName << "[] = {";
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
if ((i % 14) == 0)
O << "\n ";
void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
Record *AsmWriter = Target.getAsmWriter();
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
- const std::vector<CodeGenRegister*> &Registers =
- Target.getRegBank().getRegisters();
+ const auto &Registers = Target.getRegBank().getRegisters();
std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices();
bool hasAltNames = AltNameIndices.size() > 1;
+ std::string Namespace =
+ Registers.front().TheDef->getValueAsString("Namespace");
O <<
"\n\n/// getRegisterName - This method is automatically generated by tblgen\n"
emitRegisterNameString(O, "", Registers);
if (hasAltNames) {
- O << " const uint32_t *RegAsmOffset;\n"
- << " const char *AsmStrs;\n"
- << " switch(AltIdx) {\n"
+ O << " switch(AltIdx) {\n"
<< " default: llvm_unreachable(\"Invalid register alt name index!\");\n";
for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) {
- StringRef Namespace = AltNameIndices[1]->getValueAsString("Namespace");
- StringRef AltName(AltNameIndices[i]->getName());
- O << " case " << Namespace << "::" << AltName
- << ":\n"
- << " AsmStrs = AsmStrs" << AltName << ";\n"
- << " RegAsmOffset = RegAsmOffset" << AltName << ";\n"
- << " break;\n";
+ std::string AltName(AltNameIndices[i]->getName());
+ std::string Prefix = !Namespace.empty() ? Namespace + "::" : "";
+ O << " case " << Prefix << AltName << ":\n"
+ << " assert(*(AsmStrs" << AltName << "+RegAsmOffset"
+ << AltName << "[RegNo-1]) &&\n"
+ << " \"Invalid alt name index for register!\");\n"
+ << " return AsmStrs" << AltName << "+RegAsmOffset"
+ << AltName << "[RegNo-1];\n";
}
- O << "}\n";
+ O << " }\n";
+ } else {
+ O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
+ << " \"Invalid alt name index for register!\");\n"
+ << " return AsmStrs+RegAsmOffset[RegNo-1];\n";
}
-
- O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n"
- << " \"Invalid alt name index for register!\");\n"
- << " return AsmStrs+RegAsmOffset[RegNo-1];\n"
- << "}\n";
+ O << "}\n";
}
namespace {
// alias for that pattern.
class IAPrinter {
std::vector<std::string> Conds;
- std::map<StringRef, unsigned> OpMap;
+ std::map<StringRef, std::pair<int, int>> OpMap;
+ SmallVector<Record*, 4> ReqFeatures;
+
std::string Result;
std::string AsmString;
- SmallVector<Record*, 4> ReqFeatures;
public:
- IAPrinter(std::string R, std::string AS)
- : Result(R), AsmString(AS) {}
+ IAPrinter(std::string R, std::string AS) : Result(R), AsmString(AS) {}
void addCond(const std::string &C) { Conds.push_back(C); }
- void addOperand(StringRef Op, unsigned Idx) {
- assert(Idx < 0xFF && "Index too large!");
- OpMap[Op] = Idx;
+ void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
+ assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
+ assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF &&
+ "Idx out of range");
+ OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
}
- unsigned getOpIndex(StringRef Op) { return OpMap[Op]; }
+
bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
+ int getOpIndex(StringRef Op) { return OpMap[Op].first; }
+ std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; }
+
+ std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start,
+ StringRef::iterator End) {
+ StringRef::iterator I = Start;
+ StringRef::iterator Next;
+ if (*I == '{') {
+ // ${some_name}
+ Start = ++I;
+ while (I != End && *I != '}')
+ ++I;
+ Next = I;
+ // eat the final '}'
+ if (Next != End)
+ ++Next;
+ } else {
+ // $name, just eat the usual suspects.
+ while (I != End &&
+ ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') ||
+ (*I >= '0' && *I <= '9') || *I == '_'))
+ ++I;
+ Next = I;
+ }
+
+ return std::make_pair(StringRef(Start, I - Start), Next);
+ }
void print(raw_ostream &O) {
if (Conds.empty() && ReqFeatures.empty()) {
// Directly mangle mapped operands into the string. Each operand is
// identified by a '$' sign followed by a byte identifying the number of the
// operand. We add one to the index to avoid zero bytes.
- std::pair<StringRef, StringRef> ASM = StringRef(AsmString).split(' ');
- SmallString<128> OutString = ASM.first;
- if (!ASM.second.empty()) {
- raw_svector_ostream OS(OutString);
- OS << ' ';
- for (StringRef::iterator I = ASM.second.begin(), E = ASM.second.end();
- I != E;) {
- OS << *I;
- if (*I == '$') {
- StringRef::iterator Start = ++I;
- while (I != E &&
- ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') ||
- (*I >= '0' && *I <= '9') || *I == '_'))
- ++I;
- StringRef Name(Start, I - Start);
- assert(isOpMapped(Name) && "Unmapped operand!");
- OS << format("\\x%02X", (unsigned char)getOpIndex(Name) + 1);
- } else {
- ++I;
- }
+ StringRef ASM(AsmString);
+ SmallString<128> OutString;
+ raw_svector_ostream OS(OutString);
+ for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) {
+ OS << *I;
+ if (*I == '$') {
+ StringRef Name;
+ std::tie(Name, I) = parseName(++I, E);
+ assert(isOpMapped(Name) && "Unmapped operand!");
+
+ int OpIndex, PrintIndex;
+ std::tie(OpIndex, PrintIndex) = getOpData(Name);
+ if (PrintIndex == -1) {
+ // Can use the default printOperand route.
+ OS << format("\\x%02X", (unsigned char)OpIndex + 1);
+ } else
+ // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand
+ // number, and which of our pre-detected Methods to call.
+ OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
+ } else {
+ ++I;
}
}
// Emit the string.
- O.indent(6) << "AsmString = \"" << OutString.str() << "\";\n";
+ O.indent(6) << "AsmString = \"" << OutString << "\";\n";
O.indent(6) << "break;\n";
O.indent(4) << '}';
}
- bool operator==(const IAPrinter &RHS) {
+ bool operator==(const IAPrinter &RHS) const {
if (Conds.size() != RHS.Conds.size())
return false;
unsigned Idx = 0;
- for (std::vector<std::string>::iterator
- I = Conds.begin(), E = Conds.end(); I != E; ++I)
- if (*I != RHS.Conds[Idx++])
+ for (const auto &str : Conds)
+ if (str != RHS.Conds[Idx++])
return false;
return true;
}
-
- bool operator()(const IAPrinter &RHS) {
- if (Conds.size() < RHS.Conds.size())
- return true;
-
- unsigned Idx = 0;
- for (std::vector<std::string>::iterator
- I = Conds.begin(), E = Conds.end(); I != E; ++I)
- if (*I != RHS.Conds[Idx++])
- return *I < RHS.Conds[Idx++];
-
- return false;
- }
};
} // end anonymous namespace
-static unsigned CountNumOperands(StringRef AsmString) {
- unsigned NumOps = 0;
- std::pair<StringRef, StringRef> ASM = AsmString.split(' ');
+static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) {
+ std::string FlatAsmString =
+ CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant);
+ AsmString = FlatAsmString;
- while (!ASM.second.empty()) {
- ++NumOps;
- ASM = ASM.second.split(' ');
- }
-
- return NumOps;
+ return AsmString.count(' ') + AsmString.count('\t');
}
-static unsigned CountResultNumOperands(StringRef AsmString) {
- unsigned NumOps = 0;
- std::pair<StringRef, StringRef> ASM = AsmString.split('\t');
-
- if (!ASM.second.empty()) {
- size_t I = ASM.second.find('{');
- StringRef Str = ASM.second;
- if (I != StringRef::npos)
- Str = ASM.second.substr(I, ASM.second.find('|', I));
-
- ASM = Str.split(' ');
+namespace {
+struct AliasPriorityComparator {
+ typedef std::pair<CodeGenInstAlias, int> ValueType;
+ bool operator()(const ValueType &LHS, const ValueType &RHS) {
+ if (LHS.second == RHS.second) {
+ // We don't actually care about the order, but for consistency it
+ // shouldn't depend on pointer comparisons.
+ return LHS.first.TheDef->getName() < RHS.first.TheDef->getName();
+ }
- do {
- ++NumOps;
- ASM = ASM.second.split(' ');
- } while (!ASM.second.empty());
+ // Aliases with larger priorities should be considered first.
+ return LHS.second > RHS.second;
}
-
- return NumOps;
+};
}
+
void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
Record *AsmWriter = Target.getAsmWriter();
O << "\n#ifdef PRINT_ALIAS_INSTR\n";
O << "#undef PRINT_ALIAS_INSTR\n\n";
+ //////////////////////////////
+ // Gather information about aliases we need to print
+ //////////////////////////////
+
// Emit the method that prints the alias instruction.
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
+ unsigned Variant = AsmWriter->getValueAsInt("Variant");
+ unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget");
std::vector<Record*> AllInstAliases =
Records.getAllDerivedDefinitions("InstAlias");
// Create a map from the qualified name to a list of potential matches.
- std::map<std::string, std::vector<CodeGenInstAlias*> > AliasMap;
+ typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator>
+ AliasWithPriority;
+ std::map<std::string, AliasWithPriority> AliasMap;
for (std::vector<Record*>::iterator
I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) {
- CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Target);
const Record *R = *I;
- if (!R->getValueAsBit("EmitAlias"))
- continue; // We were told not to emit the alias, but to emit the aliasee.
+ int Priority = R->getValueAsInt("EmitPriority");
+ if (Priority < 1)
+ continue; // Aliases with priority 0 are never emitted.
+
const DagInit *DI = R->getValueAsDag("ResultInst");
const DefInit *Op = cast<DefInit>(DI->getOperator());
- AliasMap[getQualifiedName(Op->getDef())].push_back(Alias);
+ AliasMap[getQualifiedName(Op->getDef())].insert(
+ std::make_pair(CodeGenInstAlias(*I, Variant, Target), Priority));
}
// A map of which conditions need to be met for each instruction operand
// before it can be matched to the mnemonic.
- std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap;
+ std::map<std::string, std::vector<IAPrinter>> IAPrinterMap;
- for (std::map<std::string, std::vector<CodeGenInstAlias*> >::iterator
- I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) {
- std::vector<CodeGenInstAlias*> &Aliases = I->second;
+ // A list of MCOperandPredicates for all operands in use, and the reverse map
+ std::vector<const Record*> MCOpPredicates;
+ DenseMap<const Record*, unsigned> MCOpPredicateMap;
- for (std::vector<CodeGenInstAlias*>::iterator
- II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) {
- const CodeGenInstAlias *CGA = *II;
- unsigned LastOpNo = CGA->ResultInstOperandIndex.size();
+ for (auto &Aliases : AliasMap) {
+ for (auto &Alias : Aliases.second) {
+ const CodeGenInstAlias &CGA = Alias.first;
+ unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
unsigned NumResultOps =
- CountResultNumOperands(CGA->ResultInst->AsmString);
+ CountNumOperands(CGA.ResultInst->AsmString, Variant);
// Don't emit the alias if it has more operands than what it's aliasing.
- if (NumResultOps < CountNumOperands(CGA->AsmString))
+ if (NumResultOps < CountNumOperands(CGA.AsmString, Variant))
continue;
- IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(),
- CGA->AsmString);
+ IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString);
+
+ unsigned NumMIOps = 0;
+ for (auto &Operand : CGA.ResultOperands)
+ NumMIOps += Operand.getMINumOperands();
std::string Cond;
- Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo);
- IAP->addCond(Cond);
+ Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps);
+ IAP.addCond(Cond);
bool CantHandle = false;
+ unsigned MIOpNum = 0;
for (unsigned i = 0, e = LastOpNo; i != e; ++i) {
- const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i];
+ std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")";
+
+ const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
switch (RO.Kind) {
case CodeGenInstAlias::ResultOperand::K_Record: {
const Record *Rec = RO.getRecord();
StringRef ROName = RO.getName();
-
+ int PrintMethodIdx = -1;
+
+ // These two may have a PrintMethod, which we want to record (if it's
+ // the first time we've seen it) and provide an index for the aliasing
+ // code to use.
+ if (Rec->isSubClassOf("RegisterOperand") ||
+ Rec->isSubClassOf("Operand")) {
+ std::string PrintMethod = Rec->getValueAsString("PrintMethod");
+ if (PrintMethod != "" && PrintMethod != "printOperand") {
+ PrintMethodIdx = std::find(PrintMethods.begin(),
+ PrintMethods.end(), PrintMethod) -
+ PrintMethods.begin();
+ if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
+ PrintMethods.push_back(PrintMethod);
+ }
+ }
if (Rec->isSubClassOf("RegisterOperand"))
Rec = Rec->getValueAsDef("RegClass");
if (Rec->isSubClassOf("RegisterClass")) {
- Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()";
- IAP->addCond(Cond);
+ IAP.addCond(Op + ".isReg()");
- if (!IAP->isOpMapped(ROName)) {
- IAP->addOperand(ROName, i);
- Record *R = CGA->ResultOperands[i].getRecord();
+ if (!IAP.isOpMapped(ROName)) {
+ IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
+ Record *R = CGA.ResultOperands[i].getRecord();
if (R->isSubClassOf("RegisterOperand"))
R = R->getValueAsDef("RegClass");
Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" +
- R->getName() + "RegClassID)"
- ".contains(MI->getOperand(" + llvm::utostr(i) + ").getReg())";
- IAP->addCond(Cond);
+ R->getName() + "RegClassID)"
+ ".contains(" + Op + ".getReg())";
} else {
- Cond = std::string("MI->getOperand(") +
- llvm::utostr(i) + ").getReg() == MI->getOperand(" +
- llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()";
- IAP->addCond(Cond);
+ Cond = Op + ".getReg() == MI->getOperand(" +
+ llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()";
}
} else {
- assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
- // FIXME: We may need to handle these situations.
- delete IAP;
- IAP = 0;
- CantHandle = true;
- break;
+ // Assume all printable operands are desired for now. This can be
+ // overridden in the InstAlias instantiation if necessary.
+ IAP.addOperand(ROName, MIOpNum, PrintMethodIdx);
+
+ // There might be an additional predicate on the MCOperand
+ unsigned Entry = MCOpPredicateMap[Rec];
+ if (!Entry) {
+ if (!Rec->isValueUnset("MCOperandPredicate")) {
+ MCOpPredicates.push_back(Rec);
+ Entry = MCOpPredicates.size();
+ MCOpPredicateMap[Rec] = Entry;
+ } else
+ break; // No conditions on this operand at all
+ }
+ Cond = Target.getName() + ClassName + "ValidateMCOperand(" +
+ Op + ", STI, " + llvm::utostr(Entry) + ")";
}
-
+ // for all subcases of ResultOperand::K_Record:
+ IAP.addCond(Cond);
break;
}
case CodeGenInstAlias::ResultOperand::K_Imm: {
- std::string Op = "MI->getOperand(" + llvm::utostr(i) + ")";
-
// Just because the alias has an immediate result, doesn't mean the
// MCInst will. An MCExpr could be present, for example.
- IAP->addCond(Op + ".isImm()");
+ IAP.addCond(Op + ".isImm()");
- Cond = Op + ".getImm() == "
- + llvm::utostr(CGA->ResultOperands[i].getImm());
- IAP->addCond(Cond);
+ Cond = Op + ".getImm() == " +
+ llvm::utostr(CGA.ResultOperands[i].getImm());
+ IAP.addCond(Cond);
break;
}
case CodeGenInstAlias::ResultOperand::K_Reg:
// If this is zero_reg, something's playing tricks we're not
// equipped to handle.
- if (!CGA->ResultOperands[i].getRegister()) {
+ if (!CGA.ResultOperands[i].getRegister()) {
CantHandle = true;
break;
}
- Cond = std::string("MI->getOperand(") +
- llvm::utostr(i) + ").getReg() == " + Target.getName() +
- "::" + CGA->ResultOperands[i].getRegister()->getName();
- IAP->addCond(Cond);
+ Cond = Op + ".getReg() == " + Target.getName() + "::" +
+ CGA.ResultOperands[i].getRegister()->getName();
+ IAP.addCond(Cond);
break;
}
- if (!IAP) break;
+ MIOpNum += RO.getMINumOperands();
}
if (CantHandle) continue;
- IAPrinterMap[I->first].push_back(IAP);
+ IAPrinterMap[Aliases.first].push_back(std::move(IAP));
}
}
+ //////////////////////////////
+ // Write out the printAliasInstr function
+ //////////////////////////////
+
std::string Header;
raw_string_ostream HeaderO(Header);
HeaderO << "bool " << Target.getName() << ClassName
<< "::printAliasInstr(const MCInst"
- << " *MI, raw_ostream &OS) {\n";
+ << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
+ << "raw_ostream &OS) {\n";
std::string Cases;
raw_string_ostream CasesO(Cases);
- for (std::map<std::string, std::vector<IAPrinter*> >::iterator
- I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) {
- std::vector<IAPrinter*> &IAPs = I->second;
+ for (auto &Entry : IAPrinterMap) {
+ std::vector<IAPrinter> &IAPs = Entry.second;
std::vector<IAPrinter*> UniqueIAPs;
- for (std::vector<IAPrinter*>::iterator
- II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) {
- IAPrinter *LHS = *II;
+ for (auto &LHS : IAPs) {
bool IsDup = false;
- for (std::vector<IAPrinter*>::iterator
- III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) {
- IAPrinter *RHS = *III;
- if (LHS != RHS && *LHS == *RHS) {
+ for (const auto &RHS : IAPs) {
+ if (&LHS != &RHS && LHS == RHS) {
IsDup = true;
break;
}
}
- if (!IsDup) UniqueIAPs.push_back(LHS);
+ if (!IsDup)
+ UniqueIAPs.push_back(&LHS);
}
if (UniqueIAPs.empty()) continue;
- CasesO.indent(2) << "case " << I->first << ":\n";
+ CasesO.indent(2) << "case " << Entry.first << ":\n";
for (std::vector<IAPrinter*>::iterator
II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) {
return;
}
+ if (!MCOpPredicates.empty())
+ O << "static bool " << Target.getName() << ClassName
+ << "ValidateMCOperand(const MCOperand &MCOp,\n"
+ << " const MCSubtargetInfo &STI,\n"
+ << " unsigned PredicateIndex);\n";
+
O << HeaderO.str();
O.indent(2) << "const char *AsmString;\n";
O.indent(2) << "switch (MI->getOpcode()) {\n";
// Code that prints the alias, replacing the operands with the ones from the
// MCInst.
O << " unsigned I = 0;\n";
- O << " while (AsmString[I] != ' ' && AsmString[I] != '\\0')\n";
+ O << " while (AsmString[I] != ' ' && AsmString[I] != '\t' &&\n";
+ O << " AsmString[I] != '\\0')\n";
O << " ++I;\n";
O << " OS << '\\t' << StringRef(AsmString, I);\n";
O << " do {\n";
O << " if (AsmString[I] == '$') {\n";
O << " ++I;\n";
- O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n";
+ O << " if (AsmString[I] == (char)0xff) {\n";
+ O << " ++I;\n";
+ O << " int OpIdx = AsmString[I++] - 1;\n";
+ O << " int PrintMethodIdx = AsmString[I++] - 1;\n";
+ O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, ";
+ O << (PassSubtarget ? "STI, " : "");
+ O << "OS);\n";
+ O << " } else\n";
+ O << " printOperand(MI, unsigned(AsmString[I++]) - 1, ";
+ O << (PassSubtarget ? "STI, " : "");
+ O << "OS);\n";
O << " } else {\n";
O << " OS << AsmString[I++];\n";
O << " }\n";
O << " return true;\n";
O << "}\n\n";
+ //////////////////////////////
+ // Write out the printCustomAliasOperand function
+ //////////////////////////////
+
+ O << "void " << Target.getName() << ClassName << "::"
+ << "printCustomAliasOperand(\n"
+ << " const MCInst *MI, unsigned OpIdx,\n"
+ << " unsigned PrintMethodIdx,\n"
+ << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "")
+ << " raw_ostream &OS) {\n";
+ if (PrintMethods.empty())
+ O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n";
+ else {
+ O << " switch (PrintMethodIdx) {\n"
+ << " default:\n"
+ << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"
+ << " break;\n";
+
+ for (unsigned i = 0; i < PrintMethods.size(); ++i) {
+ O << " case " << i << ":\n"
+ << " " << PrintMethods[i] << "(MI, OpIdx, "
+ << (PassSubtarget ? "STI, " : "") << "OS);\n"
+ << " break;\n";
+ }
+ O << " }\n";
+ }
+ O << "}\n\n";
+
+ if (!MCOpPredicates.empty()) {
+ O << "static bool " << Target.getName() << ClassName
+ << "ValidateMCOperand(const MCOperand &MCOp,\n"
+ << " const MCSubtargetInfo &STI,\n"
+ << " unsigned PredicateIndex) {\n"
+ << " switch (PredicateIndex) {\n"
+ << " default:\n"
+ << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n"
+ << " break;\n";
+
+ for (unsigned i = 0; i < MCOpPredicates.size(); ++i) {
+ Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate");
+ if (StringInit *SI = dyn_cast<StringInit>(MCOpPred)) {
+ O << " case " << i + 1 << ": {\n"
+ << SI->getValue() << "\n"
+ << " }\n";
+ } else
+ llvm_unreachable("Unexpected MCOperandPredicate field!");
+ }
+ O << " }\n"
+ << "}\n\n";
+ }
+
O << "#endif // PRINT_ALIAS_INSTR\n";
}
AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) {
Record *AsmWriter = Target.getAsmWriter();
- for (CodeGenTarget::inst_iterator I = Target.inst_begin(),
- E = Target.inst_end();
- I != E; ++I)
- if (!(*I)->AsmString.empty() && (*I)->TheDef->getName() != "PHI")
- Instructions.push_back(
- AsmWriterInst(**I, AsmWriter->getValueAsInt("Variant"),
- AsmWriter->getValueAsInt("OperandSpacing")));
+ for (const CodeGenInstruction *I : Target.instructions())
+ if (!I->AsmString.empty() && I->TheDef->getName() != "PHI")
+ Instructions.emplace_back(*I, AsmWriter->getValueAsInt("Variant"),
+ AsmWriter->getValueAsInt("PassSubtarget"));
// Get the instruction numbering.
NumberedInstructions = &Target.getInstructionsByEnumValue();
projects / oota-llvm.git / blobdiff