Don't depend on the order relocations are written to a .o file.

[oota-llvm.git] / test / MC / ARM / eh-directive-section-multiple-func.s

diff --git a/test/MC/ARM/eh-directive-section-multiple-func.s b/test/MC/ARM/eh-directive-section-multiple-func.s
index 425cbd7d0158ba4157362ce121ea36ff885abec0..e7198a4aecbeac2dde56f44a0cd50abd5b9be6c5 100644 (file)
--- a/test/MC/ARM/eh-directive-section-multiple-func.s
+++ b/test/MC/ARM/eh-directive-section-multiple-func.s
@@ -1,5 +1,7 @@
 @ RUN: llvm-mc %s -triple=armv7-unknown-linux-gnueabi -filetype=obj -o - \
-@ RUN:   | llvm-readobj -s -sd -sr -t | FileCheck %s
+@ RUN:   | llvm-readobj -s -sd -sr -t > %t
+@ RUN: FileCheck %s < %t
+@ RUN: FileCheck --check-prefix=RELOC %s < %t
 
 @ Check whether the section is switched back properly.
 
@@ -70,13 +72,13 @@ func2:
 @ CHECK:     )
 @ CHECK:   }
 
-@ CHECK:   Section {
-@ CHECK:     Name: .rel.ARM.extab.TEST1
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK:       0x8 R_ARM_PREL31 __gxx_personality_v0 0x0
-@ CHECK:     ]
-@ CHECK:   }
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.extab.TEST1
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC:       0x8 R_ARM_PREL31 __gxx_personality_v0 0x0
+@ RELOC:     ]
+@ RELOC:   }
 
 
 @-------------------------------------------------------------------------------
@@ -99,15 +101,15 @@ func2:
 @ .ARM.extab.TESET1 section.
 @-------------------------------------------------------------------------------
 
-@ CHECK:   Section {
-@ CHECK:     Name: .rel.ARM.exidx.TEST1
-@ CHECK:     Relocations [
-@ CHECK:       0x0 R_ARM_PREL31 .TEST1 0x0
-@ CHECK:       0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK:       0x8 R_ARM_PREL31 .TEST1 0x0
-@ CHECK:       0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0
-@ CHECK:     ]
-@ CHECK:   }
+@ RELOC:   Section {
+@ RELOC:     Name: .rel.ARM.exidx.TEST1
+@ RELOC:     Relocations [
+@ RELOC:       0x0 R_ARM_PREL31 .TEST1 0x0
+@ RELOC:       0x4 R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC:       0x8 R_ARM_PREL31 .TEST1 0x0
+@ RELOC:       0xC R_ARM_PREL31 .ARM.extab.TEST1 0x0
+@ RELOC:     ]
+@ RELOC:   }
 
 
 @-------------------------------------------------------------------------------