; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.olt.s $[[CC:f0]], $[[F2]], $[[F3]]
+; 32R6: cmp.lt.s $[[CC:f0]], $[[F2]], $[[F3]]
; 32R6: sel.s $[[CC]], $f14, $f12
; 64: c.olt.s $f14, $f15
; 64R2: movt.s $f13, $f12, $fcc0
; 64R2: mov.s $f0, $f13
-; 64R6: cmp.olt.s $[[CC:f0]], $f14, $f15
+; 64R6: cmp.lt.s $[[CC:f0]], $f14, $f15
; 64R6: sel.s $[[CC]], $f13, $f12
%cmp = fcmp olt float %f2, %f3
; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.olt.s $[[CC:f0]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
; 32R6: sel.s $[[CC]], $f14, $f12
; 64: c.ule.s $f14, $f15
; 64R2: movf.s $f13, $f12, $fcc0
; 64R2: mov.s $f0, $f13
-; 64R6: cmp.olt.s $[[CC:f0]], $f15, $f14
+; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14
; 64R6: sel.s $[[CC]], $f13, $f12
%cmp = fcmp ogt float %f2, %f3
; 32R6-DAG: lwc1 $[[F2:f[0-9]+]], 16($sp)
; 32R6-DAG: lwc1 $[[F3:f[0-9]+]], 20($sp)
-; 32R6: cmp.olt.s $[[CC:f0]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.s $[[CC:f0]], $[[F3]], $[[F2]]
; 32R6: sel.d $[[CC]], $f14, $f12
; 64: c.ule.s $f14, $f15
; 64R2: movf.d $f13, $f12, $fcc0
; 64R2: mov.d $f0, $f13
-; 64R6: cmp.olt.s $[[CC:f0]], $f15, $f14
+; 64R6: cmp.lt.s $[[CC:f0]], $f15, $f14
; 64R6: sel.d $[[CC]], $f13, $f12
%cmp = fcmp ogt float %f2, %f3
; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R6: cmp.olt.d $[[CC:f0]], $[[F2]], $[[F3]]
+; 32R6: cmp.lt.d $[[CC:f0]], $[[F2]], $[[F3]]
; 32R6: sel.d $[[CC]], $f14, $f12
; 64: c.olt.d $f14, $f15
; 64R2: movt.d $f13, $f12, $fcc0
; 64R2: mov.d $f0, $f13
-; 64R6: cmp.olt.d $[[CC:f0]], $f14, $f15
+; 64R6: cmp.lt.d $[[CC:f0]], $f14, $f15
; 64R6: sel.d $[[CC]], $f13, $f12
%cmp = fcmp olt double %f2, %f3
; 32R6-DAG: ldc1 $[[F2:f[0-9]+]], 16($sp)
; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 24($sp)
-; 32R6: cmp.olt.d $[[CC:f0]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
; 32R6: sel.d $[[CC]], $f14, $f12
; 64: c.ule.d $f14, $f15
; 64R2: movf.d $f13, $f12, $fcc0
; 64R2: mov.d $f0, $f13
-; 64R6: cmp.olt.d $[[CC:f0]], $f15, $f14
+; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14
; 64R6: sel.d $[[CC]], $f13, $f12
%cmp = fcmp ogt double %f2, %f3
; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mthc1 $7, $[[F2]]
; 32R6-DAG: ldc1 $[[F3:f[0-9]+]], 16($sp)
-; 32R6: cmp.olt.d $[[CC:f0]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.d $[[CC:f0]], $[[F3]], $[[F2]]
; 32R6: sel.s $[[CC]], $f14, $f12
; 64: c.ule.d $f14, $f15
; 64R2: movf.s $f13, $f12, $fcc0
; 64R2: mov.s $f0, $f13
-; 64R6: cmp.olt.d $[[CC:f0]], $f15, $f14
+; 64R6: cmp.lt.d $[[CC:f0]], $f15, $f14
; 64R6: sel.s $[[CC]], $f13, $f12
%cmp = fcmp ogt double %f2, %f3
; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.olt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
+; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
; 64R2: movt $5, $4, $fcc0
; 64R2: move $2, $5
-; 64R6: cmp.olt.s $[[CC:f[0-9]+]], $f14, $f15
+; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f14, $f15
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
; 32R6-DAG: mtc1 $6, $[[F2:f[0-9]+]]
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
-; 32R6: cmp.olt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]]
+; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
; 64R2: movf $5, $4, $fcc0
; 64R2: move $2, $5
-; 64R6: cmp.olt.s $[[CC:f[0-9]+]], $f15, $f14
+; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f15, $f14
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R6: cmp.olt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
+; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R6: cmp.olt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
+; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
; 32R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
; 32R6-DAG: lw $[[D3:[0-9]+]], %got(d3)($1)
; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 32R6: cmp.olt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
+; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant
; 64R6-DAG: ldc1 $[[TMP:f[0-9]+]], 0($[[D2]])
; 64R6-DAG: ld $[[D3:[0-9]+]], %got_disp(d3)($1)
; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
-; 64R6: cmp.olt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
+; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
; FIXME: This move is redundant