[DAGCombiner] Attempt to mask vectors before zero extension instead of after.

[oota-llvm.git] / test / CodeGen / AArch64 / arm64-arith.ll

diff --git a/test/CodeGen/AArch64/arm64-arith.ll b/test/CodeGen/AArch64/arm64-arith.ll
index f36e706b15ddaaef5f51dbe536450da5a2175733..d5d9a1b98174b3baafa6d633cbda45194a998067 100644 (file)
--- a/test/CodeGen/AArch64/arm64-arith.ll
+++ b/test/CodeGen/AArch64/arm64-arith.ll
@@ -123,7 +123,8 @@ entry:
 define i64 @t14(i16 %a, i64 %x) nounwind ssp {
 entry:
 ; CHECK-LABEL: t14:
-; CHECK: add   x0, x1, w0, uxth #3
+; CHECK: and   w8, w0, #0xffff
+; CHECK: add   x0, x1, w8, uxtw #3
 ; CHECK: ret
   %c = zext i16 %a to i64
   %d = shl i64 %c, 3