[AArch64] Fix bug in prolog clobbering live reg when shrink wrapping.

[oota-llvm.git] / test / CodeGen / AArch64 / aarch64-dynamic-stack-layout.ll

diff --git a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
index f33211eadd287e8538de3c0a631c4796793be5e0..90093f94d0ad985e156cc0e65b2a85dfb3fd10d8 100644 (file)
--- a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
+++ b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
@@ -1,4 +1,4 @@
-; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -disable-post-ra < %s | FileCheck %s
 
 ; This test aims to check basic correctness of frame layout &
 ; frame access code. There are 8 functions in this test file,
@@ -252,11 +252,11 @@ entry:
 ; CHECK: ldr   w[[IARG:[0-9]+]], [x29, #24]
 ; CHECK: ldr   d[[DARG:[0-9]+]], [x29, #40]
 ;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
-; CHECK: ubfx  x9, x0, #0, #32
+; CHECK: mov   w9, w0
+; CHECK: mov    x10, sp
 ; CHECK: lsl   x9, x9, #2
 ; CHECK: add   x9, x9, #15
 ; CHECK: and   x9, x9, #0x7fffffff0
-; CHECK: mov    x10, sp
 ; CHECK: sub    x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov    sp, x[[VLASPTMP]]
 ;   Check correct access to local variable, through frame pointer
@@ -299,11 +299,11 @@ entry:
 ; CHECK: ldr   w[[IARG:[0-9]+]], [x29, #24]
 ; CHECK: ldr   d[[DARG:[0-9]+]], [x29, #40]
 ;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
-; CHECK: ubfx  x9, x0, #0, #32
+; CHECK: mov   w9, w0
+; CHECK: mov    x10, sp
 ; CHECK: lsl   x9, x9, #2
 ; CHECK: add   x9, x9, #15
 ; CHECK: and   x9, x9, #0x7fffffff0
-; CHECK: mov    x10, sp
 ; CHECK: sub    x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov    sp, x[[VLASPTMP]]
 ;   Check correct access to local variable, through frame pointer
@@ -361,11 +361,11 @@ entry:
 ; CHECK: ldr   d[[DARG:[0-9]+]], [x29, #40]
 ;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
 ;   and set-up of base pointer (x19).
-; CHECK: ubfx  x9, x0, #0, #32
+; CHECK: mov   w9, w0
+; CHECK: mov    x10, sp
 ; CHECK: lsl   x9, x9, #2
 ; CHECK: add   x9, x9, #15
 ; CHECK: and   x9, x9, #0x7fffffff0
-; CHECK: mov    x10, sp
 ; CHECK: sub    x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov    sp, x[[VLASPTMP]]
 ;   Check correct access to local variable, through base pointer
@@ -414,11 +414,11 @@ entry:
 ; CHECK: ldr   d[[DARG:[0-9]+]], [x29, #40]
 ;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
 ;   and set-up of base pointer (x19).
-; CHECK: ubfx  x9, x0, #0, #32
+; CHECK: mov   w9, w0
+; CHECK: mov    x10, sp
 ; CHECK: lsl   x9, x9, #2
 ; CHECK: add   x9, x9, #15
 ; CHECK: and   x9, x9, #0x7fffffff0
-; CHECK: mov    x10, sp
 ; CHECK: sub    x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov    sp, x[[VLASPTMP]]
 ;   Check correct access to local variable, through base pointer
@@ -465,11 +465,11 @@ entry:
 ; CHECK: ldr   d[[DARG:[0-9]+]], [x29, #40]
 ;   Check correct reservation of 16-byte aligned VLA (size in w0) on stack
 ;   and set-up of base pointer (x19).
-; CHECK: ubfx  x9, x0, #0, #32
+; CHECK: mov   w9, w0
+; CHECK: mov    x10, sp
 ; CHECK: lsl   x9, x9, #2
 ; CHECK: add   x9, x9, #15
 ; CHECK: and   x9, x9, #0x7fffffff0
-; CHECK: mov    x10, sp
 ; CHECK: sub    x[[VLASPTMP:[0-9]+]], x10, x9
 ; CHECK: mov    sp, x[[VLASPTMP]]
 ;   Check correct access to local variable, through base pointer
@@ -482,6 +482,56 @@ entry:
 ; CHECK: ldp   x20, x19, [sp], #32
 ; CHECK: ret
 
+
+define void @realign_conditional(i1 %b) {
+entry:
+  br i1 %b, label %bb0, label %bb1
+
+bb0:
+  %MyAlloca = alloca i8, i64 64, align 32
+  br label %bb1
+
+bb1:
+  ret void
+}
+
+; CHECK-LABEL: realign_conditional
+; No realignment in the prologue.
+; CHECK-NOT:  and
+; CHECK-NOT:  0xffffffffffffffe0
+; CHECK:  tbz  {{.*}} .[[LABEL:.*]]
+; Stack is realigned in a non-entry BB.
+; CHECK:  sub  [[REG:x[01-9]+]], sp, #64
+; CHECK:  and  sp, [[REG]], #0xffffffffffffffe0
+; CHECK:  .[[LABEL]]:
+; CHECK:  ret
+
+
+define void @realign_conditional2(i1 %b) {
+entry:
+  %tmp = alloca i8, i32 4
+  br i1 %b, label %bb0, label %bb1
+
+bb0:
+  %MyAlloca = alloca i8, i64 64, align 32
+  br label %bb1
+
+bb1:
+  ret void
+}
+
+; CHECK-LABEL: realign_conditional2
+; Extra realignment in the prologue (performance issue).
+; CHECK:  sub  x9, sp, #32            // =32
+; CHECK:  and  sp, x9, #0xffffffffffffffe0
+; CHECK:  mov   x19, sp
+; CHECK:  tbz  {{.*}} .[[LABEL:.*]]
+; Stack is realigned in a non-entry BB.
+; CHECK:  sub  [[REG:x[01-9]+]], sp, #64
+; CHECK:  and  sp, [[REG]], #0xffffffffffffffe0
+; CHECK:  .[[LABEL]]:
+; CHECK:  ret
+
 attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }