{ ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
{ ISD::SHL, MVT::v2i64, 2*10 }, // Scalarized.
{ ISD::SHL, MVT::v4i64, 4*10 }, // Scalarized.
-\r
- { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence.\r
- { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence.\r
- { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend.\r
- { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.\r
-\r
- { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence.\r
- { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence.\r
- { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend.\r
- { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.\r
-\r
- // It is not a good idea to vectorize division. We have to scalarize it and\r
+
+ { ISD::SRL, MVT::v16i8, 26 }, // cmpgtb sequence.
+ { ISD::SRL, MVT::v8i16, 32 }, // cmpgtb sequence.
+ { ISD::SRL, MVT::v4i32, 16 }, // Shift each lane + blend.
+ { ISD::SRL, MVT::v2i64, 2*10 }, // Scalarized.
+
+ { ISD::SRA, MVT::v16i8, 54 }, // unpacked cmpgtb sequence.
+ { ISD::SRA, MVT::v8i16, 32 }, // cmpgtb sequence.
+ { ISD::SRA, MVT::v4i32, 16 }, // Shift each lane + blend.
+ { ISD::SRA, MVT::v2i64, 2*10 }, // Scalarized.
+
+ // It is not a good idea to vectorize division. We have to scalarize it and
// in the process we will often end up having to spilling regular
// registers. The overhead of division is going to dominate most kernels
// anyways so try hard to prevent vectorization of division - it is
}
return X86TTIImpl::getIntImmCost(Imm, Ty);
}
-\r
-bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, int Consecutive) {\r
- int DataWidth = DataTy->getPrimitiveSizeInBits();\r
- \r
- // Todo: AVX512 allows gather/scatter, works with strided and random as well\r
- if ((DataWidth < 32) || (Consecutive == 0))\r
- return false;\r
- if (ST->hasAVX512() || ST->hasAVX2()) \r
- return true;\r
- return false;\r
-}\r
+
+bool X86TTIImpl::isLegalMaskedLoad(Type *DataTy, int Consecutive) {
+ int DataWidth = DataTy->getPrimitiveSizeInBits();
+
+ // Todo: AVX512 allows gather/scatter, works with strided and random as well
+ if ((DataWidth < 32) || (Consecutive == 0))
+ return false;
+ if (ST->hasAVX512() || ST->hasAVX2())
+ return true;
+ return false;
+}
bool X86TTIImpl::isLegalMaskedStore(Type *DataType, int Consecutive) {
return isLegalMaskedLoad(DataType, Consecutive);