return new WebAssemblyRegStackify();
}
+// Decorate the given instruction with implicit operands that enforce the
+// expression stack ordering constraints.
+static void ImposeStackOrdering(MachineInstr *MI) {
+ // Read and write the opaque EXPR_STACK register.
+ MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
+ /*isDef=*/true,
+ /*isImp=*/true));
+ MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
+ /*isDef=*/false,
+ /*isImp=*/true));
+}
+
bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "********** Register Stackifying **********\n"
"********** Function: "
// Iterate through the inputs in reverse order, since we'll be pulling
// operands off the stack in FIFO order.
+ bool AnyStackified = false;
for (MachineOperand &Op : reverse(Insert->uses())) {
// We're only interested in explicit virtual register operands.
if (!Op.isReg() || Op.isImplicit())
continue;
Changed = true;
+ AnyStackified = true;
if (OneUse) {
// Move the def down and nest it in the current instruction.
MBB.insert(MachineBasicBlock::instr_iterator(Insert),
Def->removeFromParent());
MFI.stackifyVReg(Reg);
+ ImposeStackOrdering(Def);
Insert = Def;
} else {
// Clone the def down and nest it in the current instruction.
Clone->getOperand(0).setReg(NewReg);
MBB.insert(MachineBasicBlock::instr_iterator(Insert), Clone);
MFI.stackifyVReg(Reg);
+ ImposeStackOrdering(Clone);
Insert = Clone;
}
}
+ if (AnyStackified)
+ ImposeStackOrdering(&MI);
}
}
+ // If we used EXPR_STACK anywhere, add it to the live-in sets everywhere
+ // so that it never looks like a use-before-def.
+ if (Changed) {
+ MF.getRegInfo().addLiveIn(WebAssembly::EXPR_STACK);
+ for (MachineBasicBlock &MBB : MF)
+ MBB.addLiveIn(WebAssembly::EXPR_STACK);
+ }
+
return Changed;
}