#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOptions.h"
-
using namespace llvm;
#define DEBUG_TYPE "wasm-lower"
namespace {
// Diagnostic information for unimplemented or unsupported feature reporting.
-// FIXME copied from BPF and AMDGPU.
-class DiagnosticInfoUnsupported : public DiagnosticInfo {
+// TODO: This code is copied from BPF and AMDGPU; consider factoring it out
+// and sharing code.
+class DiagnosticInfoUnsupported final : public DiagnosticInfo {
private:
// Debug location where this diagnostic is triggered.
DebugLoc DLoc;
computeRegisterProperties(Subtarget->getRegisterInfo());
setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
+ setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
setOperationAction(ISD::JumpTable, MVTPtr, Custom);
for (auto T : {MVT::f32, MVT::f64}) {
setOperationAction(Op, T, Expand);
// Note supported floating-point library function operators that otherwise
// default to expand.
- for (auto Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT,
- ISD::FRINT})
+ for (auto Op :
+ {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
setOperationAction(Op, T, Legal);
// Support minnan and maxnan, which otherwise default to expand.
setOperationAction(ISD::FMINNAN, T, Legal);
for (auto T : {MVT::i32, MVT::i64}) {
// Expand unavailable integer operations.
- for (auto Op : {ISD::BSWAP, ISD::ROTL, ISD::ROTR,
- ISD::SMUL_LOHI, ISD::UMUL_LOHI,
- ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM,
- ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
- ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {
+ for (auto Op :
+ {ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
+ ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
+ ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
+ ISD::SUBE}) {
setOperationAction(Op, T, Expand);
}
}
}
bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
- const GlobalAddressSDNode *GA) const {
+ const GlobalAddressSDNode * /*GA*/) const {
// The WebAssembly target doesn't support folding offsets into global
// addresses.
return false;
}
-MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
+MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
EVT VT) const {
return VT.getSimpleVT();
}
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':
- return std::make_pair(0U, &WebAssembly::I32RegClass);
+ if (VT == MVT::i32)
+ return std::make_pair(0U, &WebAssembly::I32RegClass);
+ if (VT == MVT::i64)
+ return std::make_pair(0U, &WebAssembly::I64RegClass);
+ break;
default:
break;
}
return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
}
+bool WebAssemblyTargetLowering::isCheapToSpeculateCttz() const {
+ // Assume ctz is a relatively cheap operation.
+ return true;
+}
+
+bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const {
+ // Assume clz is a relatively cheap operation.
+ return true;
+}
+
//===----------------------------------------------------------------------===//
// WebAssembly Lowering private implementation.
//===----------------------------------------------------------------------===//
MachineFunction &MF = DAG.getMachineFunction();
CallingConv::ID CallConv = CLI.CallConv;
- if (CallConv != CallingConv::C &&
- CallConv != CallingConv::Fast &&
+ if (CallConv != CallingConv::C && CallConv != CallingConv::Fast &&
CallConv != CallingConv::Cold)
fail(DL, DAG,
"WebAssembly doesn't support language-specific or target-specific "
Chain = Res.getValue(1);
}
- // FIXME: handle CLI.RetSExt and CLI.RetZExt?
-
Chain = DAG.getCALLSEQ_END(Chain, NB, Zero, SDValue(), DL);
return Chain;
}
bool WebAssemblyTargetLowering::CanLowerReturn(
- CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
- const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+ CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
+ LLVMContext & /*Context*/) const {
// WebAssembly can't currently handle returning tuples.
return Outs.size() <= 1;
}
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
SelectionDAG &DAG) const {
- MachineFunction &MF = DAG.getMachineFunction();
-
assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
if (CallConv != CallingConv::C)
fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
// Record the number and types of the return values.
for (const ISD::OutputArg &Out : Outs) {
- if (Out.Flags.isZExt())
- fail(DL, DAG, "WebAssembly hasn't implemented zext results");
- if (Out.Flags.isSExt())
- fail(DL, DAG, "WebAssembly hasn't implemented sext results");
- if (Out.Flags.isInReg())
- fail(DL, DAG, "WebAssembly hasn't implemented inreg results");
- if (Out.Flags.isSRet())
- fail(DL, DAG, "WebAssembly hasn't implemented sret results");
- if (Out.Flags.isByVal())
- fail(DL, DAG, "WebAssembly hasn't implemented byval results");
+ assert(!Out.Flags.isByVal() && "byval is not valid for return values");
+ assert(!Out.Flags.isNest() && "nest is not valid for return values");
if (Out.Flags.isInAlloca())
fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
- if (Out.Flags.isNest())
- fail(DL, DAG, "WebAssembly hasn't implemented nest results");
- if (Out.Flags.isReturned())
- fail(DL, DAG, "WebAssembly hasn't implemented returned results");
if (Out.Flags.isInConsecutiveRegs())
fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
if (Out.Flags.isInConsecutiveRegsLast())
fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
if (!Out.IsFixed)
fail(DL, DAG, "WebAssembly doesn't support non-fixed results yet");
- MF.getInfo<WebAssemblyFunctionInfo>()->addResult(Out.VT);
}
return Chain;
if (IsVarArg)
fail(DL, DAG, "WebAssembly doesn't support varargs yet");
- unsigned ArgNo = 0;
+ // Set up the incoming ARGUMENTS value, which serves to represent the liveness
+ // of the incoming values before they're represented by virtual registers.
+ MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
+
for (const ISD::InputArg &In : Ins) {
- if (In.Flags.isZExt())
- fail(DL, DAG, "WebAssembly hasn't implemented zext arguments");
- if (In.Flags.isSExt())
- fail(DL, DAG, "WebAssembly hasn't implemented sext arguments");
- if (In.Flags.isInReg())
- fail(DL, DAG, "WebAssembly hasn't implemented inreg arguments");
- if (In.Flags.isSRet())
- fail(DL, DAG, "WebAssembly hasn't implemented sret arguments");
if (In.Flags.isByVal())
fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
if (In.Flags.isInAlloca())
fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
if (In.Flags.isNest())
fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
- if (In.Flags.isReturned())
- fail(DL, DAG, "WebAssembly hasn't implemented returned arguments");
if (In.Flags.isInConsecutiveRegs())
fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
if (In.Flags.isInConsecutiveRegsLast())
fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
- // FIXME Do something with In.getOrigAlign()?
+ // Ignore In.getOrigAlign() because all our arguments are passed in
+ // registers.
InVals.push_back(
In.Used
? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
- DAG.getTargetConstant(ArgNo, DL, MVT::i32))
+ DAG.getTargetConstant(InVals.size(), DL, MVT::i32))
: DAG.getNode(ISD::UNDEF, DL, In.VT));
// Record the number and types of arguments.
MF.getInfo<WebAssemblyFunctionInfo>()->addParam(In.VT);
- ++ArgNo;
}
return Chain;
return SDValue();
case ISD::GlobalAddress:
return LowerGlobalAddress(Op, DAG);
+ case ISD::ExternalSymbol:
+ return LowerExternalSymbol(Op, DAG);
case ISD::JumpTable:
return LowerJumpTable(Op, DAG);
case ISD::BR_JT:
DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT));
}
+SDValue
+WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ const auto *ES = cast<ExternalSymbolSDNode>(Op);
+ EVT VT = Op.getValueType();
+ assert(ES->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
+ return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
+ DAG.getTargetExternalSymbol(ES->getSymbol(), VT));
+}
+
SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
SelectionDAG &DAG) const {
// There's no need for a Wrapper node because we always incorporate a jump
- // table operand into a SWITCH instruction, rather than ever materializing
- // it in a register.
+ // table operand into a TABLESWITCH instruction, rather than ever
+ // materializing it in a register.
const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
JT->getTargetFlags());
for (auto MBB : MBBs)
Ops.push_back(DAG.getBasicBlock(MBB));
- return DAG.getNode(WebAssemblyISD::SWITCH, DL, MVT::Other, Ops);
+ return DAG.getNode(WebAssemblyISD::TABLESWITCH, DL, MVT::Other, Ops);
}
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
- const GlobalValue *GV, SectionKind Kind, Mangler &Mang,
- const TargetMachine &TM) const {
+ const GlobalValue *GV, SectionKind /*Kind*/, Mangler & /*Mang*/,
+ const TargetMachine & /*TM*/) const {
// TODO: Be more sophisticated than this.
return isa<Function>(GV) ? getTextSection() : getDataSection();
}
projects / oota-llvm.git / blobdiff