[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing...

[oota-llvm.git] / lib / Target / Hexagon / MCTargetDesc / HexagonMCTargetDesc.cpp

diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
index 53305d85fd80a34f504b98b67ac6a14b84d5afe5..c407e7cb1662786a9c01dbc71861dfc7118eba96 100644 (file)
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp
@@ -40,6 +40,14 @@ using namespace llvm;
 #define GET_REGINFO_MC_DESC
 #include "HexagonGenRegisterInfo.inc"
 
+cl::opt<bool> llvm::HexagonDisableCompound
+  ("mno-compound",
+   cl::desc("Disable looking for compound instructions for Hexagon"));
+
+cl::opt<bool> llvm::HexagonDisableDuplex
+  ("mno-pairing",
+   cl::desc("Disable looking for duplex instructions for Hexagon"));
+
 MCInstrInfo *llvm::createHexagonMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitHexagonMCInstrInfo(X);
@@ -54,7 +62,10 @@ static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) {
 
 static MCSubtargetInfo *
 createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
-  return createHexagonMCSubtargetInfoImpl(TT, CPU, FS);
+  StringRef CPUName = CPU;
+  if (CPU.empty())
+    CPUName = "hexagonv5";
+  return createHexagonMCSubtargetInfoImpl(TT, CPUName, FS);
 }
 
 namespace {