//
//===----------------------------------------------------------------------===//
-let neverHasSideEffects = 1 in
+let hasSideEffects = 0 in
class T_Immext<dag ins> :
EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
Requires<[HasV4T]>;
// ALU32 +
//===----------------------------------------------------------------------===//
// Generate frame index addresses.
-let neverHasSideEffects = 1, isReMaterializable = 1,
+let hasSideEffects = 0, isReMaterializable = 1,
isExtended = 1, opExtendable = 2, validSubTargets = HasV4SubT in
def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
(ins IntRegs:$src1, s32Imm:$offset),
// Combine
// Rdd=combine(Rs, #s8)
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 8,
- neverHasSideEffects = 1, validSubTargets = HasV4SubT in
+ hasSideEffects = 0, validSubTargets = HasV4SubT in
def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
(ins IntRegs:$src1, s8Ext:$src2),
"$dst = combine($src1, #$src2)",
// Rdd=combine(#s8, Rs)
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
- neverHasSideEffects = 1, validSubTargets = HasV4SubT in
+ hasSideEffects = 0, validSubTargets = HasV4SubT in
def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
(ins s8Ext:$src1, IntRegs:$src2),
"$dst = combine(#$src1, $src2)",
Requires<[HasV4T]>;
let isExtendable = 1, opExtendable = 2, isExtentSigned = 0, opExtentBits = 6,
- neverHasSideEffects = 1, validSubTargets = HasV4SubT in
+ hasSideEffects = 0, validSubTargets = HasV4SubT in
def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
(ins s8Imm:$src1, u6Ext:$src2),
"$dst = combine(#$src1, #$src2)",
//===----------------------------------------------------------------------===//
// Template class for load instructions with Absolute set addressing mode.
//===----------------------------------------------------------------------===//
-let isExtended = 1, opExtendable = 2, neverHasSideEffects = 1,
+let isExtended = 1, opExtendable = 2, hasSideEffects = 0,
validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
class T_LD_abs_set<string mnemonic, RegisterClass RC>:
LDInst2<(outs RC:$dst1, IntRegs:$dst2),
}
}
-let neverHasSideEffects = 1 in
+let hasSideEffects = 0 in
multiclass ld_idxd_shl<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_indexed_shl in {
let isPredicable = 1 in
}
}
-let addrMode = BaseRegOffset, neverHasSideEffects = 1,
+let addrMode = BaseRegOffset, hasSideEffects = 0,
validSubTargets = HasV4SubT in {
let accessSize = ByteAccess in
defm STrib_indexed_shl: ST_Idxd_shl<"memb", "STrib", IntRegs>,
}
}
-let isExtendable = 1, isExtentSigned = 1, neverHasSideEffects = 1 in
+let isExtendable = 1, isExtentSigned = 1, hasSideEffects = 0 in
multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_imm in {
let opExtendable = 2, opExtentBits = 8, isPredicable = 1 in
// TODO: Needs to be implemented.
// Store predicate:
-let neverHasSideEffects = 1 in
+let hasSideEffects = 0 in
def STriw_pred_V4 : STInst2<(outs),
(ins MEMri:$addr, PredRegs:$src1),
"Error; should not emit",
}
}
-let mayStore = 1, isNVStore = 1, neverHasSideEffects = 1, isExtendable = 1 in
+let mayStore = 1, isNVStore = 1, hasSideEffects = 0, isExtendable = 1 in
multiclass ST_Idxd_nv<string mnemonic, string CextOp, RegisterClass RC,
Operand ImmOp, Operand predImmOp, bits<5> ImmBits,
bits<5> PredImmBits> {
}
}
-let mayStore = 1, isNVStore = 1, isExtendable = 1, neverHasSideEffects = 1 in
+let mayStore = 1, isNVStore = 1, isExtendable = 1, hasSideEffects = 0 in
multiclass ST_MEMri_nv<string mnemonic, string CextOp, RegisterClass RC,
bits<5> ImmBits, bits<5> PredImmBits> {
Requires<[HasV4T]>;
let opExtendable = 2, isExtentSigned = 0, opExtentBits = PredImmBits,
- neverHasSideEffects = 1, isPredicated = 1 in {
+ hasSideEffects = 0, isPredicated = 1 in {
defm Pt : ST_MEMri_Pred_nv<mnemonic, RC, 0>;
defm NotPt : ST_MEMri_Pred_nv<mnemonic, RC, 1>;
}
}
}
-let hasCtrlDep = 1, isNVStore = 1, neverHasSideEffects = 1 in
+let hasCtrlDep = 1, isNVStore = 1, hasSideEffects = 0 in
multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
Operand ImmOp> {
// if ([!]cmp.gtu(Rt,Ns.new)) jump:[n]t #r9:2
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
- Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
+ Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
defm CMPEQrr : NVJrr_base<"cmp.eq", "CMPEQ", 0b000, 0>, PredRel;
defm CMPGTrr : NVJrr_base<"cmp.gt", "CMPGT", 0b001, 0>, PredRel;
defm CMPGTUrr : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
// if ([!]cmp.gtu(Ns.new,#U5)) jump:[n]t #r9:2
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator = 1,
- Defs = [PC], neverHasSideEffects = 1, validSubTargets = HasV4SubT in {
+ Defs = [PC], hasSideEffects = 0, validSubTargets = HasV4SubT in {
defm CMPEQri : NVJri_base<"cmp.eq", "CMPEQ", 0b000>, PredRel;
defm CMPGTri : NVJri_base<"cmp.gt", "CMPGT", 0b001>, PredRel;
defm CMPGTUri : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
// if ([!]cmp.gt(Ns.new,#-1)) jump:[n]t #r9:2
let isPredicated = 1, isBranch = 1, isNewValue = 1, isTerminator=1,
- Defs = [PC], neverHasSideEffects = 1 in {
+ Defs = [PC], hasSideEffects = 0 in {
defm TSTBIT0 : NVJ_ConstImm_base<"tstbit", "TSTBIT", 0b011, "0">, PredRel;
defm CMPEQn1 : NVJ_ConstImm_base<"cmp.eq", "CMPEQ", 0b100, "-1">, PredRel;
defm CMPGTn1 : NVJ_ConstImm_base<"cmp.gt", "CMPGT", 0b101, "-1">, PredRel;
//Deallocate frame and return.
// dealloc_return
let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1,
- Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1 in {
+ Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0 in {
let validSubTargets = HasV4SubT in
def DEALLOC_RET_V4 : LD0Inst<(outs), (ins),
"dealloc_return",
// if (Ps) dealloc_return
let isReturn = 1, isTerminator = 1,
- Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
+ Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
isPredicated = 1 in {
let validSubTargets = HasV4SubT in
def DEALLOC_RET_cPt_V4 : LD0Inst<(outs),
// if (!Ps) dealloc_return
let isReturn = 1, isTerminator = 1,
- Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
+ Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
isPredicated = 1, isPredicatedFalse = 1 in {
let validSubTargets = HasV4SubT in
def DEALLOC_RET_cNotPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
// if (Ps.new) dealloc_return:nt
let isReturn = 1, isTerminator = 1,
- Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
+ Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
isPredicated = 1 in {
let validSubTargets = HasV4SubT in
def DEALLOC_RET_cdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
// if (!Ps.new) dealloc_return:nt
let isReturn = 1, isTerminator = 1,
- Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
+ Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
isPredicated = 1, isPredicatedFalse = 1 in {
let validSubTargets = HasV4SubT in
def DEALLOC_RET_cNotdnPnt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
// if (Ps.new) dealloc_return:t
let isReturn = 1, isTerminator = 1,
- Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
+ Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
isPredicated = 1 in {
let validSubTargets = HasV4SubT in
def DEALLOC_RET_cdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
// if (!Ps.new) dealloc_return:nt
let isReturn = 1, isTerminator = 1,
- Defs = [R29, R30, R31, PC], Uses = [R30], neverHasSideEffects = 1,
+ Defs = [R29, R30, R31, PC], Uses = [R30], hasSideEffects = 0,
isPredicated = 1, isPredicatedFalse = 1 in {
let validSubTargets = HasV4SubT in
def DEALLOC_RET_cNotdnPt_V4 : LD0Inst<(outs), (ins PredRegs:$src1),
}
}
-let isNVStorable = 1, isExtended = 1, neverHasSideEffects = 1 in
+let isNVStorable = 1, isExtended = 1, hasSideEffects = 0 in
multiclass ST_Abs<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
let opExtendable = 0, isPredicable = 1 in
}
}
-let mayStore = 1, isNVStore = 1, isExtended = 1, neverHasSideEffects = 1 in
+let mayStore = 1, isNVStore = 1, isExtended = 1, hasSideEffects = 0 in
multiclass ST_Abs_nv<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
let opExtendable = 0, isPredicable = 1 in
}
}
-let validSubTargets = HasV4SubT, neverHasSideEffects = 1 in {
+let validSubTargets = HasV4SubT, hasSideEffects = 0 in {
let isNVStorable = 0 in
defm STd_GP : ST_GP <"memd", "STd_GP", DoubleRegs>, PredNewRel;
}
}
-let isExtended = 1, neverHasSideEffects = 1 in
+let isExtended = 1, hasSideEffects = 0 in
multiclass LD_Abs<string mnemonic, string CextOp, RegisterClass RC> {
let CextOpcode = CextOp, BaseOpcode = CextOp#_abs in {
let opExtendable = 1, isPredicable = 1 in
// Rx=mem[bhwd](##global)
// if ([!]Pv[.new]) Rx=mem[bhwd](##global)
//===----------------------------------------------------------------------===//
-let neverHasSideEffects = 1, validSubTargets = HasV4SubT in
+let hasSideEffects = 0, validSubTargets = HasV4SubT in
multiclass LD_GP<string mnemonic, string BaseOp, RegisterClass RC> {
let BaseOpcode = BaseOp in {
let isPredicable = 1 in
Requires<[HasV4T]>;
let isExtended = 1, opExtendable = 2, AddedComplexity=50,
-neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
+hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
def TFRI_cPt_V4 : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, s16Ext:$src2),
"if($src1) $dst = #$src2",
Requires<[HasV4T]>;
let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
-neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
+hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
def TFRI_cNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, s16Ext:$src2),
"if(!$src1) $dst = #$src2",
Requires<[HasV4T]>;
let isExtended = 1, opExtendable = 2, AddedComplexity=50,
-neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
+hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
def TFRI_cdnPt_V4 : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, s16Ext:$src2),
"if($src1.new) $dst = #$src2",
Requires<[HasV4T]>;
let isExtended = 1, opExtendable = 2, AddedComplexity=50, isPredicatedFalse = 1,
-neverHasSideEffects = 1, isPredicated = 1, validSubTargets = HasV4SubT in
+hasSideEffects = 0, isPredicated = 1, validSubTargets = HasV4SubT in
def TFRI_cdnNotPt_V4 : ALU32_ri<(outs IntRegs:$dst),
(ins PredRegs:$src1, s16Ext:$src2),
"if(!$src1.new) $dst = #$src2",