#include "llvm/ADT/APFloat.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
-#include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/Regex.h"
using namespace llvm;
{"ich_elsr_el2", ICH_ELSR_EL2}
};
-AArch64SysReg::MRSMapper::MRSMapper(const FeatureBitset &FeatureBits)
+AArch64SysReg::MRSMapper::MRSMapper(uint64_t FeatureBits)
: SysRegMapper(FeatureBits) {
InstPairs = &MRSPairs[0];
NumInstPairs = llvm::array_lengthof(MRSPairs);
{"icc_sgi0r_el1", ICC_SGI0R_EL1}
};
-AArch64SysReg::MSRMapper::MSRMapper(const FeatureBitset &FeatureBits)
+AArch64SysReg::MSRMapper::MSRMapper(uint64_t FeatureBits)
: SysRegMapper(FeatureBits) {
InstPairs = &MSRPairs[0];
NumInstPairs = llvm::array_lengthof(MSRPairs);
}
// Next search for target specific registers
- if (FeatureBits[AArch64::ProcCyclone]) {
+ if (FeatureBits & AArch64::ProcCyclone) {
for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
if (CycloneSysRegPairs[i].Name == NameLower) {
Valid = true;
}
// Next search for target specific registers
- if (FeatureBits[AArch64::ProcCyclone]) {
+ if (FeatureBits & AArch64::ProcCyclone) {
for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
if (CycloneSysRegPairs[i].Value == Bits) {
return CycloneSysRegPairs[i].Name;