-//==-- AArch64Subtarget.h - Define Subtarget for the AArch64 ---*- C++ -*--===//
+//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// This file declares the AArch64 specific subclass of TargetSubtargetInfo.
+// This file declares the AArch64 specific subclass of TargetSubtarget.
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_AARCH64_SUBTARGET_H
-#define LLVM_TARGET_AARCH64_SUBTARGET_H
+#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
+#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
-#include "llvm/ADT/Triple.h"
+#include "AArch64FrameLowering.h"
+#include "AArch64ISelLowering.h"
+#include "AArch64InstrInfo.h"
+#include "AArch64RegisterInfo.h"
+#include "AArch64SelectionDAGInfo.h"
+#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetSubtargetInfo.h"
+#include <string>
#define GET_SUBTARGETINFO_HEADER
#include "AArch64GenSubtargetInfo.inc"
-#include <string>
-
namespace llvm {
-class StringRef;
class GlobalValue;
+class StringRef;
+class Triple;
class AArch64Subtarget : public AArch64GenSubtargetInfo {
- virtual void anchor();
protected:
- enum ARMProcFamilyEnum {Others, CortexA53, CortexA57};
+ enum ARMProcFamilyEnum {Others, CortexA35, CortexA53, CortexA57, Cyclone};
/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
ARMProcFamilyEnum ARMProcFamily;
+ bool HasV8_1aOps;
+ bool HasV8_2aOps;
+
bool HasFPARMv8;
bool HasNEON;
bool HasCrypto;
+ bool HasCRC;
+ bool HasPerfMon;
+ bool HasFullFP16;
+ bool HasSPE;
- /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
- /// accesses for some types. For details, see
- /// AArch64TargetLowering::allowsUnalignedMemoryAccesses().
- bool AllowsUnalignedMem;
+ // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
+ bool HasZeroCycleRegMove;
- /// TargetTriple - What processor and OS we're targeting.
- Triple TargetTriple;
+ // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
+ bool HasZeroCycleZeroing;
+
+ // StrictAlign - Disallow unaligned memory accesses.
+ bool StrictAlign;
+
+ // ReserveX18 - X18 is not available as a general purpose register.
+ bool ReserveX18;
+
+ bool IsLittle;
/// CPUString - String name of used CPU.
std::string CPUString;
- /// IsLittleEndian - The target is Little Endian
- bool IsLittleEndian;
+ /// TargetTriple - What processor and OS we're targeting.
+ Triple TargetTriple;
+ AArch64FrameLowering FrameLowering;
+ AArch64InstrInfo InstrInfo;
+ AArch64SelectionDAGInfo TSInfo;
+ AArch64TargetLowering TLInfo;
private:
- void initializeSubtargetFeatures(StringRef CPU, StringRef FS);
+ /// initializeSubtargetDependencies - Initializes using CPUString and the
+ /// passed in feature string so that we can use initializer lists for
+ /// subtarget initialization.
+ AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
public:
/// This constructor initializes the data members to match that
/// of the specified triple.
- ///
- AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS,
+ AArch64Subtarget(const Triple &TT, const std::string &CPU,
+ const std::string &FS, const TargetMachine &TM,
bool LittleEndian);
- virtual bool enableMachineScheduler() const {
- return true;
+ const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
+ return &TSInfo;
+ }
+ const AArch64FrameLowering *getFrameLowering() const override {
+ return &FrameLowering;
+ }
+ const AArch64TargetLowering *getTargetLowering() const override {
+ return &TLInfo;
+ }
+ const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
+ const AArch64RegisterInfo *getRegisterInfo() const override {
+ return &getInstrInfo()->getRegisterInfo();
+ }
+ const Triple &getTargetTriple() const { return TargetTriple; }
+ bool enableMachineScheduler() const override { return true; }
+ bool enablePostRAScheduler() const override {
+ return isGeneric() || isCortexA53() || isCortexA57();
}
- /// ParseSubtargetFeatures - Parses features string setting specified
- /// subtarget options. Definition of function is auto generated by tblgen.
- void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
+ bool hasV8_1aOps() const { return HasV8_1aOps; }
+ bool hasV8_2aOps() const { return HasV8_2aOps; }
- bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
+ bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
- bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
- bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
+ bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
+ bool requiresStrictAlign() const { return StrictAlign; }
+
+ bool isX18Reserved() const { return ReserveX18; }
bool hasFPARMv8() const { return HasFPARMv8; }
bool hasNEON() const { return HasNEON; }
bool hasCrypto() const { return HasCrypto; }
+ bool hasCRC() const { return HasCRC; }
+ /// CPU has TBI (top byte of addresses is ignored during HW address
+ /// translation) and OS enables it.
+ bool supportsAddressTopByteIgnored() const;
+
+ bool hasPerfMon() const { return HasPerfMon; }
+ bool hasFullFP16() const { return HasFullFP16; }
+ bool hasSPE() const { return HasSPE; }
+
+ bool isLittleEndian() const { return IsLittle; }
+
+ bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
+ bool isTargetIOS() const { return TargetTriple.isiOS(); }
+ bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
+ bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
+ bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
+
+ bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
+ bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
+ bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
+
+ bool isGeneric() const { return CPUString == "generic"; }
+ bool isCyclone() const { return CPUString == "cyclone"; }
+ bool isCortexA57() const { return CPUString == "cortex-a57"; }
+ bool isCortexA53() const { return CPUString == "cortex-a53"; }
+
+ bool useAA() const override { return isCortexA53(); }
+
+ /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
+ /// that still makes it profitable to inline the call.
+ unsigned getMaxInlineSizeThreshold() const { return 64; }
+
+ /// ParseSubtargetFeatures - Parses features string setting specified
+ /// subtarget options. Definition of function is auto generated by tblgen.
+ void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
+
+ /// ClassifyGlobalReference - Find the target operand flags that describe
+ /// how a global value should be referenced for the current subtarget.
+ unsigned char ClassifyGlobalReference(const GlobalValue *GV,
+ const TargetMachine &TM) const;
+
+ /// This function returns the name of a function which has an interface
+ /// like the non-standard bzero function, if such a function exists on
+ /// the current subtarget and it is considered prefereable over
+ /// memset with zero passed as the second argument. Otherwise it
+ /// returns null.
+ const char *getBZeroEntry() const;
- bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
+ void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
+ MachineInstr *end,
+ unsigned NumRegionInstrs) const override;
- bool isLittle() const { return IsLittleEndian; }
+ bool enableEarlyIfConversion() const override;
- const std::string & getCPUString() const { return CPUString; }
+ std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
};
} // End llvm namespace
-#endif // LLVM_TARGET_AARCH64_SUBTARGET_H
+#endif
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