======================
-LLVM 3.3 Release Notes
+LLVM 3.8 Release Notes
======================
.. contents::
:local:
-.. warning::
- These are in-progress notes for the upcoming LLVM 3.3 release. You may
- prefer the `LLVM 3.2 Release Notes <http://llvm.org/releases/3.2/docs
- /ReleaseNotes.html>`_.
-
Introduction
============
This document contains the release notes for the LLVM Compiler Infrastructure,
-release 3.3. Here we describe the status of LLVM, including major improvements
+release 3.8. Here we describe the status of LLVM, including major improvements
from the previous release, improvements in various subprojects of LLVM, and
some of the current users of the code. All LLVM releases may be downloaded
from the `LLVM releases web site <http://llvm.org/releases/>`_.
For more information about LLVM, including information about the latest
release, please check out the `main LLVM web site <http://llvm.org/>`_. If you
have questions or comments, the `LLVM Developer's Mailing List
-<http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev>`_ is a good place to send
+<http://lists.llvm.org/mailman/listinfo/llvm-dev>`_ is a good place to send
them.
-Note that if you are reading this file from a Subversion checkout or the main
-LLVM web page, this document applies to the *next* release, not the current
-one. To see the release notes for a specific release, please see the `releases
-page <http://llvm.org/releases/>`_.
-
Non-comprehensive list of changes in this release
=================================================
+* With this release, the minimum Windows version required for running LLVM is
+ Windows 7. Earlier versions, including Windows Vista and XP are no longer
+ supported.
-.. NOTE
- For small 1-3 sentence descriptions, just add an entry at the end of
- this list. If your description won't fit comfortably in one bullet
- point (e.g. maybe you would like to give an example of the
- functionality, or simply have a lot to talk about), see the `NOTE` below
- for adding a new subsection.
+* With this release, the autoconf build system is deprecated. It will be removed
+ in the 3.9 release. Please migrate to using CMake. For more information see:
+ `Building LLVM with CMake <CMake.html>`_
-* The CellSPU port has been removed. It can still be found in older versions.
+* We have documented our C API stability guarantees for both development and
+ release branches, as well as documented how to extend the C API. Please see
+ the `developer documentation <DeveloperPolicy.html#c-api-changes>`_ for more
+ information.
-* The IR-level extended linker APIs (for example, to link bitcode files out of
- archives) have been removed. Any existing clients of these features should
- move to using a linker with integrated LTO support.
+* The C API function ``LLVMLinkModules`` is deprecated. It will be removed in the
+ 3.9 release. Please migrate to ``LLVMLinkModules2``. Unlike the old function the
+ new one
-* LLVM and Clang's documentation has been migrated to the `Sphinx
- <http://sphinx-doc.org/>`_ documentation generation system which uses
- easy-to-write reStructuredText. See `llvm/docs/README.txt` for more
- information.
+ * Doesn't take an unused parameter.
+ * Destroys the source instead of only damaging it.
+ * Does not record a message. Use the diagnostic handler instead.
+
+* The C API functions ``LLVMParseBitcode``, ``LLVMParseBitcodeInContext``,
+ ``LLVMGetBitcodeModuleInContext`` and ``LLVMGetBitcodeModule`` have been deprecated.
+ They will be removed in 3.9. Please migrate to the versions with a 2 suffix.
+ Unlike the old ones the new ones do not record a diagnostic message. Use
+ the diagnostic handler instead.
+
+* The deprecated C APIs ``LLVMGetBitcodeModuleProviderInContext`` and
+ ``LLVMGetBitcodeModuleProvider`` have been removed.
+
+* The deprecated C APIs ``LLVMCreateExecutionEngine``, ``LLVMCreateInterpreter``,
+ ``LLVMCreateJITCompiler``, ``LLVMAddModuleProvider`` and ``LLVMRemoveModuleProvider``
+ have been removed.
+
+* With this release, the C API headers have been reorganized to improve build
+ time. Type specific declarations have been moved to Type.h, and error
+ handling routines have been moved to ErrorHandling.h. Both are included in
+ Core.h so nothing should change for projects directly including the headers,
+ but transitive dependencies may be affected.
+
+* llvm-ar now supports thin archives.
+
+* llvm doesn't produce ``.data.rel.ro.local`` or ``.data.rel`` sections anymore.
+
+* Aliases to ``available_externally`` globals are now rejected by the verifier.
+
+* The IR Linker has been split into ``IRMover`` that moves bits from one module to
+ another and Linker proper that decides what to link.
+
+* Support for dematerializing has been dropped.
+
+* ``RegisterScheduler::setDefault`` was removed. Targets that used to call into the
+ command line parser to set the ``DAGScheduler``, and that don't have enough
+ control with ``setSchedulingPreference``, should look into overriding the
+ ``SubTargetHook`` "``getDAGScheduler()``".
+
+* ``ilist_iterator<T>`` no longer has implicit conversions to and from ``T*``,
+ since ``ilist_iterator<T>`` may be pointing at the sentinel (which is usually
+ not of type ``T`` at all). To convert from an iterator ``I`` to a pointer,
+ use ``&*I``; to convert from a pointer ``P`` to an iterator, use
+ ``P->getIterator()``. Alternatively, explicit conversions via
+ ``static_cast<T>(U)`` are still available.
+
+* ``ilist_node<T>::getNextNode()`` and ``ilist_node<T>::getPrevNode()`` now
+ fail at compile time when the node cannot access its parent list.
+ Previously, when the sentinel was was an ``ilist_half_node<T>``, this API
+ could return the sentinel instead of ``nullptr``. Frustrated callers should
+ be updated to use ``iplist<T>::getNextNode(T*)`` instead. Alternatively, if
+ the node ``N`` is guaranteed not to be the last in the list, it is safe to
+ call ``&*++N->getIterator()`` directly.
+
+* The `Kaleidoscope tutorials <tutorial/index.html>`_ have been updated to use
+ the ORC JIT APIs.
+
+* ORC now has a basic set of C bindings.
+
+* Optional support for linking clang and the LLVM tools with a single libLLVM
+ shared library. To enable this, pass ``-DLLVM_LINK_LLVM_DYLIB=ON`` to CMake.
+ See `Building LLVM with CMake`_ for more details.
+
+* The optimization to move the prologue and epilogue of functions in colder
+ code path (shrink-wrapping) is now enabled by default.
+
+* A new target-independent gcc-compatible emulated Thread Local Storage mode
+ is added. When ``-femultated-tls`` flag is used, all accesses to TLS
+ variables are converted to calls to ``__emutls_get_address`` in the runtime
+ library.
+
+* MSVC-compatible exception handling has been completely overhauled. New
+ instructions have been introduced to facilitate this:
+ `New exception handling instructions <ExceptionHandling.html#new-exception-handling-instructions>`_.
+ While we have done our best to test this feature thoroughly, it would
+ not be completely surprising if there were a few lingering issues that
+ early adopters might bump into.
+
+
+Changes to the ARM Backends
+---------------------------
+
+During this release the AArch64 target has:
+
+* Added support for more sanitizers (MSAN, TSAN) and made them compatible with
+ all VMA kernel configurations (currently tested on 39 and 42 bits).
+* Gained initial LLD support in the new ELF back-end
+* Extended the Load/Store optimiser and cleaned up some of the bad decisions
+ made earlier.
+* Expanded LLDB support, including watchpoints, native building, Renderscript,
+ LLDB-server, debugging 32-bit applications.
+* Added support for the ``Exynos M1`` chip.
+
+During this release the ARM target has:
+
+* Gained massive performance improvements on embedded benchmarks due to finally
+ running the stride vectorizer in full form, incrementing the performance gains
+ that we already had in the previous releases with limited stride vectorization.
+* Expanded LLDB support, including watchpoints, unwind tables
+* Extended the Load/Store optimiser and cleaned up some of the bad decisions
+ made earlier.
+* Simplified code generation for global variable addresses in ELF, resulting in
+ a significant (4% in Chromium) reduction in code size.
+* Gained some additional code size improvements, though there's still a long road
+ ahead, especially for older cores.
+* Added some EABI floating point comparison functions to Compiler-RT
+* Added support for Windows+GNU triple, ``+features`` in ``-mcpu``/``-march`` options.
+
+
+Changes to the MIPS Target
+--------------------------
-* TargetTransformInfo (TTI) is a new interface that can be used by IR-level
- passes to obtain target-specific information, such as the costs of
- instructions. Only "Lowering" passes such as LSR and the vectorizer are
- allowed to use the TTI infrastructure.
+During this release the MIPS target has:
-* We've improved the X86 and ARM cost model.
+* Significantly extended support for the Integrated Assembler. See below for
+ more information
+* Added support for the ``P5600`` processor.
+* Added support for the ``interrupt`` attribute for MIPS32R2 and later. This
+ attribute will generate a function which can be used as a interrupt handler
+ on bare metal MIPS targets using the static relocation model.
+* Added support for the ``ERETNC`` instruction found in MIPS32R5 and later.
+* Added support for OpenCL. See http://portablecl.org/.
-* The Attributes classes have been completely rewritten and expanded. They now
- support not only enumerated attributes and alignments, but "string"
- attributes, which are useful for passing information to code generation. See
- :doc:`HowToUseAttributes` for more details.
+* Address spaces 1 to 255 are now reserved for software use and conversions
+ between them are no-op casts.
-* TableGen's syntax for instruction selection patterns has been simplified.
- Instead of specifying types indirectly with register classes, you should now
- specify types directly in the input patterns. See ``SparcInstrInfo.td`` for
- examples of the new syntax. The old syntax using register classes still
- works, but it will be removed in a future LLVM release.
+* Removed the ``mips16`` value for the ``-mcpu`` option since it is an :abbr:`ASE
+ (Application Specific Extension)` and not a processor. If you were using this,
+ please specify another CPU and use ``-mips16`` to enable MIPS16.
+* Removed ``copy_u.w`` from 32-bit MSA and ``copy_u.d`` from 64-bit MSA since
+ they have been removed from the MSA specification due to forward compatibility
+ issues. For example, 32-bit MSA code containing ``copy_u.w`` would behave
+ differently on a 64-bit processor supporting MSA. The corresponding intrinsics
+ are still available and may expand to ``copy_s.[wd]`` where this is
+ appropriate for forward compatibility purposes.
+* Relaxed the ``-mnan`` option to allow ``-mnan=2008`` on MIPS32R2/MIPS64R2 for
+ compatibility with GCC.
+* Made MIPS64R6 the default CPU for 64-bit Android triples.
-* MCJIT now supports exception handling. Support for it in the old jit will be
- removed in the 3.4 release.
+The MIPS target has also fixed various bugs including the following notable
+fixes:
-* Command line options can now be grouped into categories which are shown in
- the output of ``-help``. See :ref:`grouping options into categories`.
+* Fixed reversed operands on ``mthi``/``mtlo`` in the DSP :abbr:`ASE
+ (Application Specific Extension)`.
+* The code generator no longer uses ``jal`` for calls to absolute immediate
+ addresses.
+* Disabled fast instruction selection on MIPS32R6 and MIPS64R6 since this is not
+ yet supported.
+* Corrected addend for ``R_MIPS_HI16`` and ``R_MIPS_PCHI16`` in MCJIT
+* The code generator no longer crashes when handling subregisters of an 64-bit
+ FPU register with undefined value.
+* The code generator no longer attempts to use ``$zero`` for operands that do
+ not permit ``$zero``.
+* Corrected the opcode used for ``ll``/``sc`` when using MIPS32R6/MIPS64R6 and
+ the Integrated Assembler.
+* Added support for atomic load and atomic store.
+* Corrected debug info when dynamically re-aligning the stack.
-* The appearance of command line options in ``-help`` that are inherited by
- linking with libraries that use the LLVM Command line support library can now
- be modified at runtime. See :ref:`cl::getRegisteredOptions`.
+We have made a large number of improvements to the integrated assembler for
+MIPS. In this release, the integrated assembler isn't quite production-ready
+since there are a few known issues related to bare-metal support, checking
+immediates on instructions, and the N32/N64 ABI's. However, the current support
+should be sufficient for many users of the O32 ABI, particularly those targeting
+MIPS32 on Linux or bare-metal MIPS32.
-* ... next change ...
+If you would like to try the integrated assembler, please use
+``-fintegrated-as``.
-.. NOTE
- If you would like to document a larger change, then you can add a
- subsection about it right here. You can copy the following boilerplate
- and un-indent it (the indentation causes it to be inside this comment).
+Changes to the PowerPC Target
+-----------------------------
- Special New Feature
- -------------------
+There are numerous improvements to the PowerPC target in this release:
- Makes programs 10x faster by doing Special New Thing.
+* Shrink wrapping optimization has been enabled for PowerPC Little Endian
-AArch64 target
---------------
+* Direct move instructions are used when converting scalars to vectors
-We've added support for AArch64, ARM's 64-bit architecture. Development is still
-in fairly early stages, but we expect successful compilation when:
+* Thread Sanitizer (TSAN) is now supported for PowerPC
-- compiling standard compliant C99 and C++03 with Clang;
-- using Linux as a target platform;
-- where code + static data doesn't exceed 4GB in size (heap allocated data has
- no limitation).
+* New MI peephole pass to clean up redundant XXPERMDI instructions
-Some additional functionality is also implemented, notably DWARF debugging,
-GNU-style thread local storage and inline assembly.
+* Add branch hints to highly biased branch instructions (code reaching
+ unreachable terminators and exceptional control flow constructs)
-Hexagon Target
---------------
+* Promote boolean return values to integer to prevent excessive usage of
+ condition registers
-- Removed support for legacy hexagonv2 and hexagonv3 processor
- architectures which are no longer in use. Currently supported
- architectures are hexagonv4 and hexagonv5.
+* Additional vector APIs for vector comparisons and vector merges have been
+ added to altivec.h
-Loop Vectorizer
----------------
+* Many bugs have been identified and fixed
-We've continued the work on the loop vectorizer. The loop vectorizer now
-has the following features:
-- Loops with unknown trip counts.
-- Runtime checks of pointers.
-- Reductions, Inductions.
-- Min/Max reductions of integers.
-- If Conversion.
-- Pointer induction variables.
-- Reverse iterators.
-- Vectorization of mixed types.
-- Vectorization of function calls.
-- Partial unrolling during vectorization.
+Changes to the X86 Target
+-----------------------------
-The loop vectorizer is now enabled by default for -O3.
+* TLS is enabled for Cygwin as emutls.
-SLP Vectorizer
---------------
+* Smaller code for materializing 32-bit 1 and -1 constants at ``-Os``.
-LLVM now has a new SLP vectorizer. The new SLP vectorizer is not enabled by
-default but can be enabled using the clang flag -fslp-vectorize. The BB-vectorizer
-can also be enabled using the command line flag -fslp-vectorize-aggressive.
+* More efficient code for wide integer compares. (E.g. 64-bit compares
+ on 32-bit targets.)
-R600 Backend
-------------
+* Tail call support for ``thiscall``, ``stdcall``, ``vectorcall``, and
+ ``fastcall`` functions.
-The R600 backend was added in this release, it supports AMD GPUs
-(HD2XXX - HD7XXX). This backend is used in AMD's Open Source
-graphics / compute drivers which are developed as part of the `Mesa3D
-<http://www.mesa3d.org>`_ project.
+Changes to the Hexagon Target
+-----------------------------
-SystemZ/s390x Backend
----------------------
+In addition to general code size and performance improvements, Hexagon target
+now has basic support for Hexagon V60 architecture and Hexagon Vector
+Extensions (HVX).
-LLVM and clang now support IBM's z/Architecture. At present this support
-is restricted to GNU/Linux (GNU triplet s390x-linux-gnu) and requires
-z10 or greater.
+Changes to the AVR Target
+-------------------------
+Slightly less than half of the AVR backend has been merged in at this point. It is still
+missing a number large parts which cause it to be unusable, but is well on the
+road to being completely merged and workable.
-External Open Source Projects Using LLVM 3.3
+Changes to the OCaml bindings
+-----------------------------
+
+* The ocaml function link_modules has been replaced with link_modules' which
+ uses LLVMLinkModules2.
+
+
+External Open Source Projects Using LLVM 3.8
============================================
An exciting aspect of LLVM is that it is used as an enabling technology for
a lot of other language and tools projects. This section lists some of the
-projects that have already been updated to work with LLVM 3.3.
-
-
-Portable Computing Language (pocl)
-----------------------------------
-
-In addition to producing an easily portable open source OpenCL
-implementation, another major goal of `pocl <http://pocl.sourceforge.net/>`_
-is improving performance portability of OpenCL programs with
-compiler optimizations, reducing the need for target-dependent manual
-optimizations. An important part of pocl is a set of LLVM passes used to
-statically parallelize multiple work-items with the kernel compiler, even in
-the presence of work-group barriers. This enables static parallelization of
-the fine-grained static concurrency in the work groups in multiple ways.
-
-TTA-based Co-design Environment (TCE)
--------------------------------------
-
-`TCE <http://tce.cs.tut.fi/>`_ is a toolset for designing new
-processors based on the Transport triggered architecture (TTA).
-The toolset provides a complete co-design flow from C/C++
-programs down to synthesizable VHDL/Verilog and parallel program binaries.
-Processor customization points include the register files, function units,
-supported operations, and the interconnection network.
-
-TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent
-optimizations and also for parts of code generation. It generates new
-LLVM-based code generators "on the fly" for the designed TTA processors and
-loads them in to the compiler backend as runtime libraries to avoid
-per-target recompilation of larger parts of the compiler chain.
-
-Just-in-time Adaptive Decoder Engine (Jade)
--------------------------------------------
-
-`Jade <https://github.com/orcc/jade>`_ (Just-in-time Adaptive Decoder Engine)
-is a generic video decoder engine using LLVM for just-in-time compilation of
-video decoder configurations. Those configurations are designed by MPEG
-Reconfigurable Video Coding (RVC) committee. MPEG RVC standard is built on a
-stream-based dataflow representation of decoders. It is composed of a standard
-library of coding tools written in RVC-CAL language and a dataflow
-configuration --- block diagram --- of a decoder.
-
-Jade project is hosted as part of the Open RVC-CAL Compiler
-(`Orcc <http://orcc.sf.net>`_) and requires it to translate the RVC-CAL standard
-library of video coding tools into an LLVM assembly code.
+projects that have already been updated to work with LLVM 3.8.
+
+LDC - the LLVM-based D compiler
+-------------------------------
+
+`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
+pragmatically combines efficiency, control, and modeling power, with safety and
+programmer productivity. D supports powerful concepts like Compile-Time Function
+Execution (CTFE) and Template Meta-Programming, provides an innovative approach
+to concurrency and offers many classical paradigms.
+
+`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
+combined with LLVM as backend to produce efficient native code. LDC targets
+x86/x86_64 systems like Linux, OS X and Windows and also PowerPC (32/64 bit)
+and ARM. Ports to other architectures like AArch64 and MIPS64 are underway.
+
Additional Information
======================
If you have any questions or comments about LLVM, please feel free to contact
us via the `mailing lists <http://llvm.org/docs/#maillist>`_.
-
projects / oota-llvm.git / blobdiff