======================
-LLVM 3.5 Release Notes
+LLVM 3.8 Release Notes
======================
.. contents::
:local:
.. warning::
- These are in-progress notes for the upcoming LLVM 3.5 release. You may
- prefer the `LLVM 3.4 Release Notes <http://llvm.org/releases/3.4/docs
+ These are in-progress notes for the upcoming LLVM 3.8 release. You may
+ prefer the `LLVM 3.7 Release Notes <http://llvm.org/releases/3.7.0/docs
/ReleaseNotes.html>`_.
============
This document contains the release notes for the LLVM Compiler Infrastructure,
-release 3.5. Here we describe the status of LLVM, including major improvements
+release 3.8. Here we describe the status of LLVM, including major improvements
from the previous release, improvements in various subprojects of LLVM, and
some of the current users of the code. All LLVM releases may be downloaded
from the `LLVM releases web site <http://llvm.org/releases/>`_.
For more information about LLVM, including information about the latest
release, please check out the `main LLVM web site <http://llvm.org/>`_. If you
have questions or comments, the `LLVM Developer's Mailing List
-<http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev>`_ is a good place to send
+<http://lists.llvm.org/mailman/listinfo/llvm-dev>`_ is a good place to send
them.
Note that if you are reading this file from a Subversion checkout or the main
Non-comprehensive list of changes in this release
=================================================
+* With this release, the minimum Windows version required for running LLVM is
+ Windows 7. Earlier versions, including Windows Vista and XP are no longer
+ supported.
-* All backends have been changed to use the MC asm printer and support for the
- non MC one has been removed.
+* With this release, the autoconf build system is deprecated. It will be removed
+ in the 3.9 release. Please migrate to using CMake. For more information see:
+ `Building LLVM with CMake <CMake.html>`_
-* Clang can now successfully self-host itself on Linux/Sparc64 and on
- FreeBSD/Sparc64.
+* The C API function LLVMLinkModules is deprecated. It will be removed in the
+ 3.9 release. Please migrate to LLVMLinkModules2. Unlike the old function the
+ new one
-* LLVM now assumes the assembler supports ``.loc`` for generating debug line
- numbers. The old support for printing the debug line info directly was only
- used by ``llc`` and has been removed.
+ * Doesn't take an unused parameter.
+ * Destroys the source instead of only damaging it.
+ * Does not record a message. Use the diagnostic handler instead.
-* All inline assembly is parsed by the integrated assembler when it is enabled.
- Previously this was only the case for object-file output. It is now the case
- for assembly output as well. The integrated assembler can be disabled with
- the ``-no-integrated-as`` option.
+* The C API functions LLVMParseBitcode, LLVMParseBitcodeInContext,
+ LLVMGetBitcodeModuleInContext and LLVMGetBitcodeModule have been deprecated.
+ They will be removed in 3.9. Please migrate to the versions with a 2 suffix.
+ Unlike the old ones the new ones do not record a diagnostic message. Use
+ the diagnostic handler instead.
-* llvm-ar now handles IR files like regular object files. In particular, a
- regular symbol table is created for symbols defined in IR files, including
- those in file scope inline assembly.
+* The deprecated C APIs LLVMGetBitcodeModuleProviderInContext and
+ LLVMGetBitcodeModuleProvider have been removed.
-* LLVM now always uses cfi directives for producing most stack
- unwinding information.
+* The deprecated C APIs LLVMCreateExecutionEngine, LLVMCreateInterpreter,
+ LLVMCreateJITCompiler, LLVMAddModuleProvider and LLVMRemoveModuleProvider
+ have been removed.
-* The prefix for loop vectorizer hint metadata has been changed from
- ``llvm.vectorizer`` to ``llvm.loop.vectorize``. In addition,
- ``llvm.vectorizer.unroll`` metadata has been renamed
- ``llvm.loop.interleave.count``.
+* With this release, the C API headers have been reorganized to improve build
+ time. Type specific declarations have been moved to Type.h, and error
+ handling routines have been moved to ErrorHandling.h. Both are included in
+ Core.h so nothing should change for projects directly including the headers,
+ but transitive dependencies may be affected.
-* Some backends previously implemented Atomic NAND(x,y) as ``x & ~y``. Now
- all backends implement it as ``~(x & y)``, matching the semantics of GCC 4.4
- and later.
+* llvm-ar now suports thin archives.
+
+* llvm doesn't produce .data.rel.ro.local or .data.rel sections anymore.
+
+* aliases to available_externally globals are now rejected by the verifier.
+
+* the IR Linker has been split into IRMover that moves bits from one module to
+ another and Linker proper that decides what to link.
+
+* Support for dematerializing has been dropped.
+
+* ``ilist_iterator<T>`` no longer has implicit conversions to and from ``T*``,
+ since ``ilist_iterator<T>`` may be pointing at the sentinel (which is usually
+ not of type ``T`` at all). To convert from an iterator ``I`` to a pointer,
+ use ``&*I``; to convert from a pointer ``P`` to an iterator, use
+ ``P->getIterator()``. Alternatively, explicit conversions via
+ ``static_cast<T>(U)`` are still available.
+
+* ``ilist_node<T>::getNextNode()`` and ``ilist_node<T>::getPrevNode()`` now
+ fail at compile time when the node cannot access its parent list.
+ Previously, when the sentinel was was an ``ilist_half_node<T>``, this API
+ could return the sentinal instead of ``nullptr``. Frustrated callers should
+ be updated to use ``iplist<T>::getNextNode(T*)`` instead. Alternatively, if
+ the node ``N`` is guaranteed not to be the last in the list, it is safe to
+ call ``&*++N->getIterator()`` directly.
.. NOTE
For small 1-3 sentence descriptions, just add an entry at the end of
Changes to the ARM Backend
--------------------------
-Since release 3.3, a lot of new features have been included in the ARM
-back-end but weren't production ready (ie. well tested) on release 3.4.
-Just after the 3.4 release, we started heavily testing two major parts
-of the back-end: the integrated assembler (IAS) and the ARM exception
-handling (EHABI), and now they are enabled by default on LLVM/Clang.
-
-The IAS received a lot of GNU extensions and directives, as well as some
-specific pre-UAL instructions. Not all remaining directives will be
-implemented, as we made judgement calls on the need versus the complexity,
-and have chosen simplicity and future compatibility where hard decisions
-had to be made. The major difference is, as stated above, the IAS validates
-all inline ASM, not just for object emission, and that cause trouble with
-some uses of inline ASM as pre-processor magic.
-
-So, while the IAS is good enough to compile large projects (including most
-of the Linux kernel), there are a few things that we can't (and probably
-won't) do. For those cases, please use ``-fno-integrated-as`` in Clang.
-
-Exception handling is another big change. After extensive testing and
-changes to cooperate with Dwarf unwinding, EHABI is enabled by default.
-The options ``-arm-enable-ehabi`` and ``-arm-enable-ehabi-descriptors``,
-which were used to enable EHABI in the previous releases, are removed now.
-
-This means all ARM code will emit EH unwind tables, or CFI unwinding (for
-debug/profiling), or both. To avoid run-time inconsistencies, C code will
-also emit EH tables (in case they interoperate with C++ code), as is the
-case for other architectures (ex. x86_64).
+ During this release ...
+
Changes to the MIPS Target
--------------------------
-There has been a large amount of improvements to the MIPS target which can be
-broken down into subtarget, ABI, and Integrated Assembler changes.
-
-Subtargets
-^^^^^^^^^^
-
-Added support for Release 6 of the MIPS32 and MIPS64 architecture (MIPS32r6
-and MIPS64r6). Release 6 makes a number of significant changes to the MIPS32
-and MIPS64 architectures. For example, FPU registers are always 64-bits wide,
-FPU NaN values conform to IEEE 754 (2008), and the unaligned memory instructions
-(such as lwl and lwr) have been replaced with a requirement for ordinary memory
-operations to support unaligned operations. Full details of MIPS32 and MIPS64
-Release 6 can be found on the `MIPS64 Architecture page at Imagination
-Technologies <http://www.imgtec.com/mips/architectures/mips64.asp>`_.
-
-This release also adds experimental support for MIPS-IV, cnMIPS, and Cavium
-Octeon CPU's.
-
-Support for the MIPS SIMD Architecture (MSA) has been improved to support MSA
-on MIPS64.
-
-Support for IEEE 754 (2008) NaN values has been added.
-
-ABI and ABI extensions
-^^^^^^^^^^^^^^^^^^^^^^
-
-There has also been considerable ABI work since the 3.4 release. This release
-adds support for the N32 ABI, the O32-FPXX ABI Extension, the O32-FP64 ABI
-Extension, and the O32-FP64A ABI Extension.
-
-The N32 ABI is an existing ABI that has now been implemented in LLVM. It is a
-64-bit ABI that is similar to N64 but retains 32-bit pointers. N64 remains the
-default 64-bit ABI in LLVM. This differs from GCC where N32 is the default
-64-bit ABI.
-
-The O32-FPXX ABI Extension is 100% compatible with the O32-ABI and the O32-FP64
-ABI Extension and may be linked with either but may not be linked with both of
-these simultaneously. It extends the O32 ABI to allow the same code to execute
-without modification on processors with 32-bit FPU registers as well as 64-bit
-FPU registers. The O32-FPXX ABI Extension is enabled by default for the O32 ABI
-on mips*-img-linux-gnu and mips*-mti-linux-gnu triples and is selected with
--mfpxx. It is expected that future releases of LLVM will enable the FPXX
-Extension for O32 on all triples.
-
-The O32-FP64 ABI Extension is an extension to the O32 ABI to fully exploit FPU's
-with 64-bit registers and is enabled with -mfp64. This replaces an undocumented
-and unsupported O32 extension which was previously enabled with -mfp64. It is
-100% compatible with the O32-FPXX ABI Extension.
-
-The O32-FP64A ABI Extension is a restricted form of the O32-FP64 ABI Extension
-which allows interlinking with unmodified binaries that use the base O32 ABI.
-
+During this release the MIPS target has:
+
+* Significantly extended support for the Integrated Assembler. See below for
+ more information
+* Added support for the ``P5600`` processor.
+* Added support for the ``interrupt`` attribute for MIPS32R2 and later. This
+ attribute will generate a function which can be used as a interrupt handler
+ on bare metal MIPS targets using the static relocation model.
+* Added support for the ``ERETNC`` instruction found in MIPS32R5 and later.
+* Added support for OpenCL. See http://portablecl.org/.
+
+ * Address spaces 1 to 255 are now reserved for software use and conversions
+ between them are no-op casts.
+
+* Removed the ``mips16`` value for the -mcpu option since it is an :abbr:`ASE
+ (Application Specific Extension)` and not a processor. If you were using this,
+ please specify another CPU and use ``-mips16`` to enable MIPS16.
+* Removed ``copy_u.w`` from 32-bit MSA and ``copy_u.d`` from 64-bit MSA since
+ they have been removed from the MSA specification due to forward compatibility
+ issues. For example, 32-bit MSA code containing ``copy_u.w`` would behave
+ differently on a 64-bit processor supporting MSA. The corresponding intrinsics
+ are still available and may expand to ``copy_s.[wd]`` where this is
+ appropriate for forward compatibility purposes.
+* Relaxed the ``-mnan`` option to allow ``-mnan=2008`` on MIPS32R2/MIPS64R2 for
+ compatibility with GCC.
+* Made MIPS64R6 the default CPU for 64-bit Android triples.
+
+The MIPS target has also fixed various bugs including the following notable
+fixes:
+
+* Fixed reversed operands on ``mthi``/``mtlo`` in the DSP :abbr:`ASE
+ (Application Specific Extension)`.
+* The code generator no longer uses ``jal`` for calls to absolute immediate
+ addresses.
+* Disabled fast instruction selection on MIPS32R6 and MIPS64R6 since this is not
+ yet supported.
+* Corrected addend for ``R_MIPS_HI16`` and ``R_MIPS_PCHI16`` in MCJIT
+* The code generator no longer crashes when handling subregisters of an 64-bit
+ FPU register with undefined value.
+* The code generator no longer attempts to use ``$zero`` for operands that do
+ not permit ``$zero``.
+* Corrected the opcode used for ``ll``/``sc`` when using MIPS32R6/MIPS64R6 and
+ the Integrated Assembler.
+* Added support for atomic load and atomic store.
+* Corrected debug info when dynamically re-aligning the stack.
+
Integrated Assembler
^^^^^^^^^^^^^^^^^^^^
+We have made a large number of improvements to the integrated assembler for
+MIPS. In this release, the integrated assembler isn't quite production-ready
+since there are a few known issues related to bare-metal support, checking
+immediates on instructions, and the N32/N64 ABI's. However, the current support
+should be sufficient for many users of the O32 ABI, particularly those targeting
+MIPS32 on Linux or bare-metal MIPS32.
-The MIPS Integrated Assembler has undergone a substantial overhaul including a
-rewrite of the assembly parser. It's not ready for general use in this release
-but adventurous users may wish to enable it using ``-fintegrated-as``.
-
-In this release, the integrated assembler supports the majority of MIPS-I,
-MIPS-II, MIPS-III, MIPS-IV, MIPS-V, MIPS32, MIPS32r2, MIPS32r6, MIPS64,
-MIPS64r2, and MIPS64r6 as well as some of the Application Specific Extensions
-such as MSA. It also supports several of the MIPS specific assembler directives
-such as ``.set``, ``.module``, ``.cpload``, etc.
+If you would like to try the integrated assembler, please use
+``-fintegrated-as``.
Changes to the PowerPC Target
-----------------------------
-The PowerPC 64-bit Little Endian subtarget (powerpc64le-unknown-linux-gnu) is
-now fully supported. This includes support for the Altivec instruction set.
+ During this release ...
-The Power Architecture 64-Bit ELFv2 ABI Specification is now supported, and
-is the default ABI for Little Endian. The ELFv1 ABI remains the default ABI
-for Big Endian. Currently, it is not possible to override these defaults.
-That capability will be available (albeit not recommended) in a future release.
-Links to the ELFv2 ABI specification and to the Power ISA Version 2.07
-specification may be found `here <https://www-03.ibm.com/technologyconnect/tgcm/TGCMServlet.wss?alias=OpenPOWER&linkid=1n0000>`_ (free registration required).
-Efforts are underway to move this to a location that doesn't require
-registration, but the planned site isn't ready yet.
+Changes to the X86 Target
+-----------------------------
-Experimental support for the VSX instruction set introduced with ISA 2.06
-is now available using the ``-mvsx`` switch. Work remains on this, so it
-is not recommended for production use. VSX is disabled for Little Endian
-regardless of this switch setting.
+ During this release ...
-Load/store cost estimates have been improved.
+* TLS is enabled for Cygwin as emutls.
-Constant hoisting has been enabled.
-Global named register support has been enabled.
+Changes to the OCaml bindings
+-----------------------------
+
+ During this release ...
+
+* The ocaml function link_modules has been replaced with link_modules' which
+ uses LLVMLinkModules2.
-Initial support for PIC code has been added for the 32-bit ELF subtarget.
-Further support will be available in a future release.
-External Open Source Projects Using LLVM 3.5
+External Open Source Projects Using LLVM 3.8
============================================
An exciting aspect of LLVM is that it is used as an enabling technology for
a lot of other language and tools projects. This section lists some of the
-projects that have already been updated to work with LLVM 3.5.
+projects that have already been updated to work with LLVM 3.8.
+
+LDC - the LLVM-based D compiler
+-------------------------------
+
+`D <http://dlang.org>`_ is a language with C-like syntax and static typing. It
+pragmatically combines efficiency, control, and modeling power, with safety and
+programmer productivity. D supports powerful concepts like Compile-Time Function
+Execution (CTFE) and Template Meta-Programming, provides an innovative approach
+to concurrency and offers many classical paradigms.
+
+`LDC <http://wiki.dlang.org/LDC>`_ uses the frontend from the reference compiler
+combined with LLVM as backend to produce efficient native code. LDC targets
+x86/x86_64 systems like Linux, OS X and Windows and also PowerPC (32/64 bit)
+and ARM. Ports to other architectures like AArch64 and MIPS64 are underway.
Additional Information
projects / oota-llvm.git / blobdiff